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JPS57154981A - Artificial interlacing circuit - Google Patents

Artificial interlacing circuit

Info

Publication number
JPS57154981A
JPS57154981A JP56041204A JP4120481A JPS57154981A JP S57154981 A JPS57154981 A JP S57154981A JP 56041204 A JP56041204 A JP 56041204A JP 4120481 A JP4120481 A JP 4120481A JP S57154981 A JPS57154981 A JP S57154981A
Authority
JP
Japan
Prior art keywords
read
shift
display
output
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56041204A
Other languages
Japanese (ja)
Other versions
JPS6343950B2 (en
Inventor
Yoshio Yasumoto
Masaaki Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56041204A priority Critical patent/JPS57154981A/en
Publication of JPS57154981A publication Critical patent/JPS57154981A/en
Publication of JPS6343950B2 publication Critical patent/JPS6343950B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)

Abstract

PURPOSE:To display the vertical direction in a smooth form, by carrying out an artificial interlace in terms of L pieces of data which are read out with overlap in case a video signal is written into a memory and then reading the video signal to enlarge it by L times for display. CONSTITUTION:A read control signal is supplied to a shift register (a) and then shifted by the clock of a horizontal synchronizing signal HD to produce shift outputs QA, QB.... The read-out clock shifted by 1H is turned into the output QB, and a delay of 1/2L-1L can have the correspondence by selecting each of the shift outpus of QA, QB... regardless of the value of L. This output is used by being switched to the original read control signal in the 1st field and to the above-mentioned shift output in the 2nd field respectively through a fieldswitching circuit (b). The circuit (b) carries out a switching operation by applying the outpus Q and Q' of an FF using a vertical synchronizing signal VD as its input to tristate buffers C1 and C2. In such way, a smooth display is possible for the video signal which is read out of a memory.
JP56041204A 1981-03-19 1981-03-19 Artificial interlacing circuit Granted JPS57154981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56041204A JPS57154981A (en) 1981-03-19 1981-03-19 Artificial interlacing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56041204A JPS57154981A (en) 1981-03-19 1981-03-19 Artificial interlacing circuit

Publications (2)

Publication Number Publication Date
JPS57154981A true JPS57154981A (en) 1982-09-24
JPS6343950B2 JPS6343950B2 (en) 1988-09-01

Family

ID=12601880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56041204A Granted JPS57154981A (en) 1981-03-19 1981-03-19 Artificial interlacing circuit

Country Status (1)

Country Link
JP (1) JPS57154981A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6446377A (en) * 1987-08-14 1989-02-20 Sony Corp Picture signal processor
JPH02226972A (en) * 1989-02-28 1990-09-10 Canon Inc Video signal processing circuit
US5387945A (en) * 1988-07-13 1995-02-07 Seiko Epson Corporation Video multiplexing system for superimposition of scalable video streams upon a background video data stream
US5929933A (en) * 1988-07-13 1999-07-27 Seiko Epson Corporation Video multiplexing system for superimposition of scalable video data streams upon a background video data stream

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105933A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Television receiver equipped with picture magnifying function
JPS5543684A (en) * 1978-09-21 1980-03-27 Mitsubishi Electric Corp Picture display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105933A (en) * 1977-02-28 1978-09-14 Hitachi Ltd Television receiver equipped with picture magnifying function
JPS5543684A (en) * 1978-09-21 1980-03-27 Mitsubishi Electric Corp Picture display device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6446377A (en) * 1987-08-14 1989-02-20 Sony Corp Picture signal processor
US5387945A (en) * 1988-07-13 1995-02-07 Seiko Epson Corporation Video multiplexing system for superimposition of scalable video streams upon a background video data stream
US5793439A (en) * 1988-07-13 1998-08-11 Seiko Epson Corporation Image control device for use in a video multiplexing system for superimposition of scalable video data streams upon a background video data stream
US5929933A (en) * 1988-07-13 1999-07-27 Seiko Epson Corporation Video multiplexing system for superimposition of scalable video data streams upon a background video data stream
US5929870A (en) * 1988-07-13 1999-07-27 Seiko Epson Corporation Video multiplexing system for superimposition of scalable video data streams upon a background video data stream
USRE37879E1 (en) 1988-07-13 2002-10-15 Seiko Epson Corporation Image control device for use in a video multiplexing system for superimposition of scalable video data streams upon a background video data stream
JPH02226972A (en) * 1989-02-28 1990-09-10 Canon Inc Video signal processing circuit

Also Published As

Publication number Publication date
JPS6343950B2 (en) 1988-09-01

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