JPS5714960A - Floppy disk control system - Google Patents
Floppy disk control systemInfo
- Publication number
- JPS5714960A JPS5714960A JP8876780A JP8876780A JPS5714960A JP S5714960 A JPS5714960 A JP S5714960A JP 8876780 A JP8876780 A JP 8876780A JP 8876780 A JP8876780 A JP 8876780A JP S5714960 A JPS5714960 A JP S5714960A
- Authority
- JP
- Japan
- Prior art keywords
- fdd
- floppy disk
- status
- register
- control system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To increase the reliability of data, by controlling a READY lamp based on the flag in a firmware and the state shift interruption given from a floppy disk controller (FDC). CONSTITUTION:An FDC1 is connected to the main side and the side of a floppy disk device (FDD) via a CPU interface 2 and an FDD interface 3 respectively. The FDD3-7 are connected with a dizzy chian. The interruption signal INT sent from an FDC11 is set to a control register 12, and the status of that moment is set to a status register 13. A firmware resets the signal INT by reading the status. The contents of interuption, the unit number of the interrupted FDD, the READY state of the FDD and others are set to the register 13.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8876780A JPS5714960A (en) | 1980-06-30 | 1980-06-30 | Floppy disk control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8876780A JPS5714960A (en) | 1980-06-30 | 1980-06-30 | Floppy disk control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5714960A true JPS5714960A (en) | 1982-01-26 |
Family
ID=13952003
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8876780A Pending JPS5714960A (en) | 1980-06-30 | 1980-06-30 | Floppy disk control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5714960A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59146799A (en) * | 1983-02-04 | 1984-08-22 | 株式会社 川島織物 | Method of detecting degree of wear of cutter edge for doublepile textile and pile cutting device for double pile textile |
-
1980
- 1980-06-30 JP JP8876780A patent/JPS5714960A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59146799A (en) * | 1983-02-04 | 1984-08-22 | 株式会社 川島織物 | Method of detecting degree of wear of cutter edge for doublepile textile and pile cutting device for double pile textile |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES487173A1 (en) | Input/output controller for a data processing system. | |
JPS57117027A (en) | Signal sending and receiving circuit | |
ES8601518A1 (en) | Data processing system including a main processor and a co-processor and co-processor error handling logic. | |
JPS5714960A (en) | Floppy disk control system | |
JPS6448160A (en) | Serial interface control system | |
JPS53135210A (en) | Data-channel switching system of asynchronous processing system | |
JPS56164357A (en) | Controller of action of copying machine | |
JPS5750059A (en) | Status history memory system | |
JPS56155453A (en) | Program execution controlling system | |
JPS5760419A (en) | Communication circuit processing system | |
JPS5760422A (en) | Data transfer controlling system | |
JPS57139833A (en) | Interruption controlling circuit | |
JPS57147762A (en) | Interruption controlling system | |
JPS6476139A (en) | Data transfer system for input/output controller | |
JPS5373934A (en) | Data exchange control system | |
JPS5662494A (en) | Switching control system for information transfer path | |
KOCZELA et al. | Adaptive voting computer system[Patent] | |
JPS5767946A (en) | Picture processor | |
JPS575137A (en) | Bus connection controlling system | |
JPS6464595A (en) | Air conditioner controller | |
JPS56145442A (en) | Multicomputer source controlling system | |
JPS5755431A (en) | Automatic power supply application device for information processing system | |
JPS56121124A (en) | Bus control system | |
JPS6448135A (en) | Asynchronous interruption control system | |
JPS56159751A (en) | Magnetic disk control system |