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JPS57143992A - Transmitting and receiving circuit for digital signal - Google Patents

Transmitting and receiving circuit for digital signal

Info

Publication number
JPS57143992A
JPS57143992A JP2840381A JP2840381A JPS57143992A JP S57143992 A JPS57143992 A JP S57143992A JP 2840381 A JP2840381 A JP 2840381A JP 2840381 A JP2840381 A JP 2840381A JP S57143992 A JPS57143992 A JP S57143992A
Authority
JP
Japan
Prior art keywords
mode
generating circuit
memory
signal
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2840381A
Other languages
Japanese (ja)
Other versions
JPS618636B2 (en
Inventor
Masaharu Kawaguchi
Yasumasa Iwase
Akira Fukui
Kaoru Tokunaga
Nobuaki Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP2840381A priority Critical patent/JPS57143992A/en
Publication of JPS57143992A publication Critical patent/JPS57143992A/en
Publication of JPS618636B2 publication Critical patent/JPS618636B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To reduce time slots and circuits in number by providing a memory area for mode holding, and by adapting all time slots to any function by receiving and holding a function switching order for every time slot. CONSTITUTION:Under the timing control of a timing pulse generating circuit 12, a mode held in a mode holding memory 202 is read out and according to the mode, a coefficient generating circuit 8 and a threshold-value generating circuit 9 are controlled to perform respective operations successively. Through transmitting operation and circuit operation by which an input signal is sent back as it is, the mode held in the memory 202 is read out. According to the read mode, a signal generating circuit 15 is controlled to generate a signal, and then a selector 17 outputs a signal transmission order which is the contents of a memory 13, and an output from corresponding one of a shift register 14, the signal generating circuit 15, and a non-calling pattern generating circuit 16 to an output terminal according to the mode held in the memory 202.
JP2840381A 1981-03-02 1981-03-02 Transmitting and receiving circuit for digital signal Granted JPS57143992A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2840381A JPS57143992A (en) 1981-03-02 1981-03-02 Transmitting and receiving circuit for digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2840381A JPS57143992A (en) 1981-03-02 1981-03-02 Transmitting and receiving circuit for digital signal

Publications (2)

Publication Number Publication Date
JPS57143992A true JPS57143992A (en) 1982-09-06
JPS618636B2 JPS618636B2 (en) 1986-03-15

Family

ID=12247693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2840381A Granted JPS57143992A (en) 1981-03-02 1981-03-02 Transmitting and receiving circuit for digital signal

Country Status (1)

Country Link
JP (1) JPS57143992A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06127661A (en) * 1992-10-21 1994-05-10 Nec Niigata Ltd Work position correction device

Also Published As

Publication number Publication date
JPS618636B2 (en) 1986-03-15

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