JPS57139859A - Error correction system - Google Patents
Error correction systemInfo
- Publication number
- JPS57139859A JPS57139859A JP56025787A JP2578781A JPS57139859A JP S57139859 A JPS57139859 A JP S57139859A JP 56025787 A JP56025787 A JP 56025787A JP 2578781 A JP2578781 A JP 2578781A JP S57139859 A JPS57139859 A JP S57139859A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- error
- circuit
- bits
- matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 abstract 4
- 238000001514 detection method Methods 0.000 abstract 1
- 208000011580 syndromic disease Diseases 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE:To improve detection rate of the error of plural bits without increasing a check bit, by detecting an error of 3 bits or more against the row direction of a fundamental matrix of 4 bits, and also making it the same circuit in byte unit. CONSTITUTION:A check bit 4 is generated against a data bit 2 in accordance with a check bit matrix which is not shown in the figure, by an additional circuit 3, and is written in a storage device 1 together with the bit 2. Subsequently, a data bit 5 and a check bit 6 are read out from the device 1, and a check bit 8 is generated in accordance with the matrix by an additional circuit 7 from the bit 5. Subsequently, it is compared 9 with the bit 6, and generates a syndrome 10. An error detecting circuit 11 decodes an error position in accordance with the matrix and sends its result 12 to a correcting circuit 13. As sor a read-out information 14 corrected by the circuit 13, an error of 1 bit is corrected and also an error of 2 bits or more in the 4 bit block is detected, as well.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56025787A JPS57139859A (en) | 1981-02-23 | 1981-02-23 | Error correction system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56025787A JPS57139859A (en) | 1981-02-23 | 1981-02-23 | Error correction system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57139859A true JPS57139859A (en) | 1982-08-30 |
JPS617654B2 JPS617654B2 (en) | 1986-03-07 |
Family
ID=12175535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56025787A Granted JPS57139859A (en) | 1981-02-23 | 1981-02-23 | Error correction system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57139859A (en) |
-
1981
- 1981-02-23 JP JP56025787A patent/JPS57139859A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS617654B2 (en) | 1986-03-07 |
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