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JPS57136237A - Driving semiconductor integrated circuit - Google Patents

Driving semiconductor integrated circuit

Info

Publication number
JPS57136237A
JPS57136237A JP56021077A JP2107781A JPS57136237A JP S57136237 A JPS57136237 A JP S57136237A JP 56021077 A JP56021077 A JP 56021077A JP 2107781 A JP2107781 A JP 2107781A JP S57136237 A JPS57136237 A JP S57136237A
Authority
JP
Japan
Prior art keywords
signal
chip
circuit
timing
ffs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56021077A
Other languages
Japanese (ja)
Inventor
Makoto Yamauchi
Susumu Yoshino
Hidehiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56021077A priority Critical patent/JPS57136237A/en
Publication of JPS57136237A publication Critical patent/JPS57136237A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1502—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs programmable

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To decrease the timing skew between multiphase clocks, by providing a driving circuit group and a built-in delaying circuit to the same semiconductor chip and connecting an external delaying circuit to realize the adjustment and then to produce the timing. CONSTITUTION:A driving circuit group is formed by connecting in parallel n sets of logical circuits 1i, 2i and 4i(i=0-n) plus a selecting circuit 3i. The timing is produced by connecting FFs 1-4 to an adjustable delaying circuit 8 containing a built-in delaying circuit 7 provided to the same semiconductor chip and an external delaying circuit 6 of the chip. The FF1 is set by an OR signal 500 of a chip selection signal 10i, and at the same time FFs 2-4 are set successively by the signal applied to the circuit 8 to be delayed to deliver the timing signal, respectively. A chip clock 31i, an chip address 33i, a chip clock 32i and a chip read/write controlling signal 34i are delivered successively by the outputs of FFs 1-4, the signal 10i, an address signal 201 and a read/write controlling signal 202, respectively.
JP56021077A 1981-02-16 1981-02-16 Driving semiconductor integrated circuit Pending JPS57136237A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56021077A JPS57136237A (en) 1981-02-16 1981-02-16 Driving semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56021077A JPS57136237A (en) 1981-02-16 1981-02-16 Driving semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57136237A true JPS57136237A (en) 1982-08-23

Family

ID=12044819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56021077A Pending JPS57136237A (en) 1981-02-16 1981-02-16 Driving semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57136237A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53113435A (en) * 1977-03-14 1978-10-03 Nec Corp Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53113435A (en) * 1977-03-14 1978-10-03 Nec Corp Memory unit

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