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JPS57133712A - Constituting method of delay circuit in master slice ic - Google Patents

Constituting method of delay circuit in master slice ic

Info

Publication number
JPS57133712A
JPS57133712A JP56019310A JP1931081A JPS57133712A JP S57133712 A JPS57133712 A JP S57133712A JP 56019310 A JP56019310 A JP 56019310A JP 1931081 A JP1931081 A JP 1931081A JP S57133712 A JPS57133712 A JP S57133712A
Authority
JP
Japan
Prior art keywords
delay circuit
master slice
inv
unit
gate electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56019310A
Other languages
English (en)
Inventor
Masayoshi Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56019310A priority Critical patent/JPS57133712A/ja
Priority to EP82300623A priority patent/EP0058504B1/en
Priority to DE8282300623T priority patent/DE3271494D1/de
Priority to US06/347,464 priority patent/US4516312A/en
Priority to IE306/82A priority patent/IE53196B1/en
Publication of JPS57133712A publication Critical patent/JPS57133712A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
JP56019310A 1981-02-12 1981-02-12 Constituting method of delay circuit in master slice ic Pending JPS57133712A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56019310A JPS57133712A (en) 1981-02-12 1981-02-12 Constituting method of delay circuit in master slice ic
EP82300623A EP0058504B1 (en) 1981-02-12 1982-02-09 Method of constructing a delay circuit in a master slice ic
DE8282300623T DE3271494D1 (en) 1981-02-12 1982-02-09 Method of constructing a delay circuit in a master slice ic
US06/347,464 US4516312A (en) 1981-02-12 1982-02-10 Method for constructing delay circuits in a master slice IC
IE306/82A IE53196B1 (en) 1981-02-12 1982-02-11 Method of constructing a delay circuit in a master slice ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019310A JPS57133712A (en) 1981-02-12 1981-02-12 Constituting method of delay circuit in master slice ic

Publications (1)

Publication Number Publication Date
JPS57133712A true JPS57133712A (en) 1982-08-18

Family

ID=11995839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019310A Pending JPS57133712A (en) 1981-02-12 1981-02-12 Constituting method of delay circuit in master slice ic

Country Status (5)

Country Link
US (1) US4516312A (ja)
EP (1) EP0058504B1 (ja)
JP (1) JPS57133712A (ja)
DE (1) DE3271494D1 (ja)
IE (1) IE53196B1 (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066449A (ja) * 1983-09-21 1985-04-16 Seiko Epson Corp ゲ−トアレ−素子
JPS60254633A (ja) * 1984-05-30 1985-12-16 Nec Corp 回路の等容量配線方式
JPS61144056A (ja) * 1984-12-18 1986-07-01 Sanyo Electric Co Ltd 半導体集積回路装置
JPS61166219A (ja) * 1985-01-18 1986-07-26 Matsushita Electric Ind Co Ltd 遅延回路
JPS61232633A (ja) * 1985-04-09 1986-10-16 Nec Corp 半導体集積回路装置
JPS6294956A (ja) * 1985-10-21 1987-05-01 Nec Corp 半導体集積回路
JPS6298641A (ja) * 1985-10-24 1987-05-08 Nec Corp 半導体集積回路
US4692783A (en) * 1983-09-30 1987-09-08 Fujitsu Limited Gate array
JPS63217820A (ja) * 1987-03-06 1988-09-09 Nec Corp Ｃｍｏｓ遅延回路
JPH01177713A (ja) * 1988-01-08 1989-07-14 Nec Corp 半導体集積回路用遅延回路
JPH01189222A (ja) * 1988-01-22 1989-07-28 Matsushita Electric Ind Co Ltd 信号遅延回路
WO1992002957A1 (fr) * 1990-08-10 1992-02-20 Seiko Epson Corporation Dispositif semi-conducteur

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4639615A (en) * 1983-12-28 1987-01-27 At&T Bell Laboratories Trimmable loading elements to control clock skew
US4633571A (en) * 1984-04-16 1987-01-06 At&T Bell Laboratories Method of manufacturing a CMOS cell array with transistor isolation
JPS61100947A (ja) * 1984-10-22 1986-05-19 Toshiba Corp 半導体集積回路装置
JPH061823B2 (ja) * 1985-11-13 1994-01-05 日本電気株式会社 半導体集積回路
US4737830A (en) * 1986-01-08 1988-04-12 Advanced Micro Devices, Inc. Integrated circuit structure having compensating means for self-inductance effects
JP2633562B2 (ja) * 1987-05-27 1997-07-23 株式会社東芝 半導体集積回路
US4812688A (en) * 1987-12-30 1989-03-14 International Business Machines Corporation Transistor delay circuits
JP2690929B2 (ja) * 1988-02-26 1997-12-17 株式会社日立製作所 Ｍｏｓトランジスタ間の配線方法
EP0650196A2 (en) * 1988-04-22 1995-04-26 Fujitsu Limited Semiconductor integrated circuit device and method of producing the same using master slice approach
CA1309781C (en) * 1988-06-21 1992-11-03 Colin Harris Compact cmos analog crosspoint switch matrix
US4959565A (en) * 1989-02-10 1990-09-25 National Semiconductor Corporation Output buffer with ground bounce control
US5037771A (en) * 1989-11-28 1991-08-06 Cross-Check Technology, Inc. Method for implementing grid-based crosscheck test structures and the structures resulting therefrom
JP2621612B2 (ja) * 1990-08-11 1997-06-18 日本電気株式会社 半導体集積回路
JP2673046B2 (ja) * 1991-01-31 1997-11-05 株式会社日立製作所 半導体集積回路配線方法
US5618744A (en) * 1992-09-22 1997-04-08 Fujitsu Ltd. Manufacturing method and apparatus of a semiconductor integrated circuit device
JPH06151704A (ja) * 1992-11-11 1994-05-31 Mitsubishi Electric Corp 半導体装置及び配置配線装置
US5986492A (en) * 1995-06-05 1999-11-16 Honeywell Inc. Delay element for integrated circuits
US5677555A (en) * 1995-12-22 1997-10-14 Cypress Semiconductor Corp. Output driver transistor with multiple gate bodies
US6014038A (en) * 1997-03-21 2000-01-11 Lightspeed Semiconductor Corporation Function block architecture for gate array
US6240542B1 (en) * 1998-07-14 2001-05-29 Lsi Logic Corporation Poly routing for chip interconnects with minimal impact on chip performance
US6399972B1 (en) 2000-03-13 2002-06-04 Oki Electric Industry Co., Ltd. Cell based integrated circuit and unit cell architecture therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039848A (ja) * 1973-08-11 1975-04-12
JPS53106532A (en) * 1977-02-28 1978-09-16 Toshiba Corp Logic circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT280348B (de) * 1968-07-30 1970-04-10 H C Hans Dipl Ing Dr Dr List Integrierter Feld-Effekt-Kettenverstärker
US3714522A (en) * 1968-11-14 1973-01-30 Kogyo Gijutsuin Agency Of Ind Semiconductor device having surface electric-field effect
US3999210A (en) * 1972-08-28 1976-12-21 Sony Corporation FET having a linear impedance characteristic over a wide range of frequency
US4157557A (en) * 1973-07-23 1979-06-05 Sony Corporation Control circuit for signal transmission
US4141023A (en) * 1973-08-11 1979-02-20 Sony Corporation Field effect transistor having a linear attenuation characteristic and an improved distortion factor with multiple gate drain contacts
US4092619A (en) * 1976-12-27 1978-05-30 Intel Corporation Mos voltage controlled lowpass filter
US4158239A (en) * 1977-12-20 1979-06-12 International Business Machines Corporation Resistive gate FET flip-flop storage cell
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
US4285001A (en) * 1978-12-26 1981-08-18 Board Of Trustees Of Leland Stanford Jr. University Monolithic distributed resistor-capacitor device and circuit utilizing polycrystalline semiconductor material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039848A (ja) * 1973-08-11 1975-04-12
JPS53106532A (en) * 1977-02-28 1978-09-16 Toshiba Corp Logic circuit

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066449A (ja) * 1983-09-21 1985-04-16 Seiko Epson Corp ゲ−トアレ−素子
US4692783A (en) * 1983-09-30 1987-09-08 Fujitsu Limited Gate array
JPS60254633A (ja) * 1984-05-30 1985-12-16 Nec Corp 回路の等容量配線方式
JPS61144056A (ja) * 1984-12-18 1986-07-01 Sanyo Electric Co Ltd 半導体集積回路装置
JPS61166219A (ja) * 1985-01-18 1986-07-26 Matsushita Electric Ind Co Ltd 遅延回路
JPH0584674B2 (ja) * 1985-04-09 1993-12-02 Nippon Electric Co
JPS61232633A (ja) * 1985-04-09 1986-10-16 Nec Corp 半導体集積回路装置
JPS6294956A (ja) * 1985-10-21 1987-05-01 Nec Corp 半導体集積回路
JPS6298641A (ja) * 1985-10-24 1987-05-08 Nec Corp 半導体集積回路
JPS63217820A (ja) * 1987-03-06 1988-09-09 Nec Corp Ｃｍｏｓ遅延回路
JPH01177713A (ja) * 1988-01-08 1989-07-14 Nec Corp 半導体集積回路用遅延回路
JPH01189222A (ja) * 1988-01-22 1989-07-28 Matsushita Electric Ind Co Ltd 信号遅延回路
WO1992002957A1 (fr) * 1990-08-10 1992-02-20 Seiko Epson Corporation Dispositif semi-conducteur

Also Published As

Publication number Publication date
IE820306L (en) 1982-08-12
EP0058504A2 (en) 1982-08-25
EP0058504A3 (en) 1983-08-31
IE53196B1 (en) 1988-08-31
EP0058504B1 (en) 1986-06-04
DE3271494D1 (en) 1986-07-10
US4516312A (en) 1985-05-14

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