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JPS57119520A - Signal-transmission switching circuit - Google Patents

Signal-transmission switching circuit

Info

Publication number
JPS57119520A
JPS57119520A JP622381A JP622381A JPS57119520A JP S57119520 A JPS57119520 A JP S57119520A JP 622381 A JP622381 A JP 622381A JP 622381 A JP622381 A JP 622381A JP S57119520 A JPS57119520 A JP S57119520A
Authority
JP
Japan
Prior art keywords
voltage
fet1
gate
switch
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP622381A
Other languages
Japanese (ja)
Inventor
Hiroshi Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teac Corp
Original Assignee
Teac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teac Corp filed Critical Teac Corp
Priority to JP622381A priority Critical patent/JPS57119520A/en
Publication of JPS57119520A publication Critical patent/JPS57119520A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To reduce variations in output DC voltage and to reduce distortion by varying the ON driving gate voltage of an FET in accordance with the voltage of a signal transmission line and by supplying a current for canceling the gate current of the FET. CONSTITUTION:In a switch-off mode where an FET1 is held OFF by turning on a transistor (TR)Q1, the output DC voltage V0 of the FET1 is nearly zero. When the TRQ1 is turned off to turn on the FET1 for a switch-on mode, a gate current Ig1 flows through a load resistance RL to generate the output DC voltage V0, but a gate current Ig1 is supplied by an FET2 constituting a gate controlling circuit to cancel the gate current Ig1 of the FET1, so that the voltage V0 is substantially zero. Therefore, no click noise is generated in a switch-on mode. Further, the gate-source bias of the FET1 is kept constant to achieve transmission in a less-distortion state.
JP622381A 1981-01-19 1981-01-19 Signal-transmission switching circuit Pending JPS57119520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP622381A JPS57119520A (en) 1981-01-19 1981-01-19 Signal-transmission switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP622381A JPS57119520A (en) 1981-01-19 1981-01-19 Signal-transmission switching circuit

Publications (1)

Publication Number Publication Date
JPS57119520A true JPS57119520A (en) 1982-07-26

Family

ID=11632513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP622381A Pending JPS57119520A (en) 1981-01-19 1981-01-19 Signal-transmission switching circuit

Country Status (1)

Country Link
JP (1) JPS57119520A (en)

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