JPS57113248A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57113248A JPS57113248A JP55187956A JP18795680A JPS57113248A JP S57113248 A JPS57113248 A JP S57113248A JP 55187956 A JP55187956 A JP 55187956A JP 18795680 A JP18795680 A JP 18795680A JP S57113248 A JPS57113248 A JP S57113248A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- groove
- forming
- sio2
- resist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To increase the density of an integrated circuit by forming an oxidized film on the surface of a groove, forming a phosphorus-silicate-glass layer in the groove, melting and forming an insulating region, thereby forming an isolating layer as the pattern. CONSTITUTION:An SiO2 layer 12 is formed on a silicon substrate 11, an Si3N4 is formed thereon, and a resist layer is formed thereon. This resist layer is patterned, a hole is opened, and a groove is formed by etching. After the resist layer is removed, an SiO2 layer 16 is formed by a thermally oxidizing method. The groove is buried with phosphrus-silicate-glass, is once molten, and an isolation layer having no crack, cavity, air bubble is formed. An SiO2 film 18 is grown on the entire surface, and the entire surface is etched.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55187956A JPS57113248A (en) | 1980-12-29 | 1980-12-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55187956A JPS57113248A (en) | 1980-12-29 | 1980-12-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57113248A true JPS57113248A (en) | 1982-07-14 |
Family
ID=16215101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55187956A Pending JPS57113248A (en) | 1980-12-29 | 1980-12-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57113248A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5955033A (en) * | 1982-09-22 | 1984-03-29 | Fujitsu Ltd | Formation of interelement isolating film |
JPS59106133A (en) * | 1982-12-09 | 1984-06-19 | Nec Corp | Integrated circuit device |
US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
JPS61194767A (en) * | 1985-02-22 | 1986-08-29 | Nec Corp | Method for manufacturing complementary MOS semiconductor device |
CN113675327A (en) * | 2021-07-23 | 2021-11-19 | 无锡莱斯能特科技有限公司 | A method of manufacturing a thermopile sensor |
-
1980
- 1980-12-29 JP JP55187956A patent/JPS57113248A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5955033A (en) * | 1982-09-22 | 1984-03-29 | Fujitsu Ltd | Formation of interelement isolating film |
JPS59106133A (en) * | 1982-12-09 | 1984-06-19 | Nec Corp | Integrated circuit device |
US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
JPS61194767A (en) * | 1985-02-22 | 1986-08-29 | Nec Corp | Method for manufacturing complementary MOS semiconductor device |
CN113675327A (en) * | 2021-07-23 | 2021-11-19 | 无锡莱斯能特科技有限公司 | A method of manufacturing a thermopile sensor |
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