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JPS57112051A - Automatic wiring design - Google Patents

Automatic wiring design

Info

Publication number
JPS57112051A
JPS57112051A JP18725480A JP18725480A JPS57112051A JP S57112051 A JPS57112051 A JP S57112051A JP 18725480 A JP18725480 A JP 18725480A JP 18725480 A JP18725480 A JP 18725480A JP S57112051 A JPS57112051 A JP S57112051A
Authority
JP
Japan
Prior art keywords
wiring
cell
cells
lattice points
points
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18725480A
Other languages
Japanese (ja)
Inventor
Shoji Sato
Satoshi Aihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18725480A priority Critical patent/JPS57112051A/en
Publication of JPS57112051A publication Critical patent/JPS57112051A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain high integration through possible decrease of wiring regions outside a cell in an LSI by a method wherein in an excessive region in a fundamental cell a wiring which can be used as a wiring between cells is provided, and processing is done so that a plurality of lattice points at the end of the wiring may be taken as equivalent points viewed from the point of designing. CONSTITUTION:On an LSI of the grid system, a wiring object 4 or the like for example which has input and output terminal at lattice points 5A, 5B is provided in the interior of a fundamental cell 1 (surrounded by the solid line), and it is used for wiring between cells for example as a part of a common wiring. For wiring within a cell, as seen in the wiring object 2', a branch 2'' is provided, and the one with disposed input and output terminals at lattice points 3A-3C may be useful. Path search process in an automatic processing for wiring between cells acknowledges lattice points 5A, 5B and 3A-3C respectively as equivalent points, and for example when 3A, 3B are selected, the wiring 2' in the interior of cell is used as the wiring between cells. By this method, in addition to possible improvement in degree of integration, wider allowance in element disposition of the fundamental cell is obtained.
JP18725480A 1980-12-29 1980-12-29 Automatic wiring design Pending JPS57112051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18725480A JPS57112051A (en) 1980-12-29 1980-12-29 Automatic wiring design

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18725480A JPS57112051A (en) 1980-12-29 1980-12-29 Automatic wiring design

Publications (1)

Publication Number Publication Date
JPS57112051A true JPS57112051A (en) 1982-07-12

Family

ID=16202744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18725480A Pending JPS57112051A (en) 1980-12-29 1980-12-29 Automatic wiring design

Country Status (1)

Country Link
JP (1) JPS57112051A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02280352A (en) * 1989-04-21 1990-11-16 Toshiba Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02280352A (en) * 1989-04-21 1990-11-16 Toshiba Corp Semiconductor integrated circuit device

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