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JPS57108911A - Clock signal control system - Google Patents

Clock signal control system

Info

Publication number
JPS57108911A
JPS57108911A JP55187142A JP18714280A JPS57108911A JP S57108911 A JPS57108911 A JP S57108911A JP 55187142 A JP55187142 A JP 55187142A JP 18714280 A JP18714280 A JP 18714280A JP S57108911 A JPS57108911 A JP S57108911A
Authority
JP
Japan
Prior art keywords
signal
clock signal
reset
clock
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55187142A
Other languages
Japanese (ja)
Other versions
JPS5826051B2 (en
Inventor
Teruo Aizawa
Minoru Etsuno
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187142A priority Critical patent/JPS5826051B2/en
Publication of JPS57108911A publication Critical patent/JPS57108911A/en
Publication of JPS5826051B2 publication Critical patent/JPS5826051B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To reset flip-flop circuits completely by supplying a reset signal to the flip-flop circuits while no clock signal arrives. CONSTITUTION:A reset signal inputted to a reset-signal input terminal 2 is supplied to all of flip-flop circuits 3-7 to be reset. The circuits 3-7 synchronize with a clock signal A inputted to a clock-signal input terminal 1 and controls the clock signal A to be supplied to said circuits. A clock-signal distributing circuit 9 consists of negative input AND gates 9-1-9-N, and is supplied with a clock signal B as a substituted with the clock signal A.
JP55187142A 1980-12-25 1980-12-25 Clock signal control method Expired JPS5826051B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55187142A JPS5826051B2 (en) 1980-12-25 1980-12-25 Clock signal control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187142A JPS5826051B2 (en) 1980-12-25 1980-12-25 Clock signal control method

Publications (2)

Publication Number Publication Date
JPS57108911A true JPS57108911A (en) 1982-07-07
JPS5826051B2 JPS5826051B2 (en) 1983-05-31

Family

ID=16200850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187142A Expired JPS5826051B2 (en) 1980-12-25 1980-12-25 Clock signal control method

Country Status (1)

Country Link
JP (1) JPS5826051B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8042074B2 (en) 2007-08-24 2011-10-18 Renesas Electronics Corporation Circuit design device, circuit design program, and circuit design method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8042074B2 (en) 2007-08-24 2011-10-18 Renesas Electronics Corporation Circuit design device, circuit design program, and circuit design method

Also Published As

Publication number Publication date
JPS5826051B2 (en) 1983-05-31

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