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JPS57106960A - Data processor with interruption control facility - Google Patents

Data processor with interruption control facility

Info

Publication number
JPS57106960A
JPS57106960A JP18257380A JP18257380A JPS57106960A JP S57106960 A JPS57106960 A JP S57106960A JP 18257380 A JP18257380 A JP 18257380A JP 18257380 A JP18257380 A JP 18257380A JP S57106960 A JPS57106960 A JP S57106960A
Authority
JP
Japan
Prior art keywords
interruption
control information
information field
register
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18257380A
Other languages
Japanese (ja)
Inventor
Shigeki Yamada
Masayoshi Matsushita
Mitsuru Fujisawa
Takeshi Masuda
Yoshihiro Ukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP18257380A priority Critical patent/JPS57106960A/en
Publication of JPS57106960A publication Critical patent/JPS57106960A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To improve the efficiency of interruption, to speed processing, and to make the interruption flexible, by automatically securing a work area, used by the stand-by and interruption processing program of a register during interruption, through hardware. CONSTITUTION:In an interruption processing program, the 1st control information field WAS for specifying a register RSA to be enqueued in a stack and the 2nd control information field RSP for specifying the size of a work area WA used by the interruption processing program are provided. Once interruption is caused, the contents of the register are enqueued in the register stand-by area RSA in the stack in accordance with the 1st control information field WAS, and the work area WA is secured in the stack in accordance with the 2nd control information field RSP.
JP18257380A 1980-12-23 1980-12-23 Data processor with interruption control facility Pending JPS57106960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18257380A JPS57106960A (en) 1980-12-23 1980-12-23 Data processor with interruption control facility

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18257380A JPS57106960A (en) 1980-12-23 1980-12-23 Data processor with interruption control facility

Publications (1)

Publication Number Publication Date
JPS57106960A true JPS57106960A (en) 1982-07-03

Family

ID=16120634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18257380A Pending JPS57106960A (en) 1980-12-23 1980-12-23 Data processor with interruption control facility

Country Status (1)

Country Link
JP (1) JPS57106960A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287732A (en) * 1989-04-28 1990-11-27 Nec Corp Register address generating device
JPH056281A (en) * 1990-10-04 1993-01-14 Nec Corp Information processor
JPH07265795A (en) * 1994-03-30 1995-10-17 Shigeharu Endo Separating device for boulder mixed in gathered gravel, sand and the like
JP2001209549A (en) * 2000-01-07 2001-08-03 Motorola Inc Device for executing context switching and its method
JP2010250817A (en) * 2009-04-08 2010-11-04 Intel Corp Redirection of inter-processor interruption in system management mode

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287732A (en) * 1989-04-28 1990-11-27 Nec Corp Register address generating device
JPH056281A (en) * 1990-10-04 1993-01-14 Nec Corp Information processor
JPH07265795A (en) * 1994-03-30 1995-10-17 Shigeharu Endo Separating device for boulder mixed in gathered gravel, sand and the like
JP2001209549A (en) * 2000-01-07 2001-08-03 Motorola Inc Device for executing context switching and its method
JP2010250817A (en) * 2009-04-08 2010-11-04 Intel Corp Redirection of inter-processor interruption in system management mode

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