JPS57106217A - Receiver - Google Patents
ReceiverInfo
- Publication number
- JPS57106217A JPS57106217A JP18320780A JP18320780A JPS57106217A JP S57106217 A JPS57106217 A JP S57106217A JP 18320780 A JP18320780 A JP 18320780A JP 18320780 A JP18320780 A JP 18320780A JP S57106217 A JPS57106217 A JP S57106217A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- broadcast
- received
- receiving
- pll
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/18—Automatic scanning over a band of frequencies
- H03J7/20—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element
- H03J7/28—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers
- H03J7/285—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers the counter or frequency divider being used in a phase locked loop
Landscapes
- Circuits Of Receivers In General (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
PURPOSE:To tune a receiver to a correct frequency, by stopping scanning of the receiving frequency when a PLL is locked. CONSTITUTION:When an up switch Su is turned on, a scanning counter 31 is counted up to raise the receiving frequency step by step. If no broadcast is received, an F/F circuit 35 is not reset to continue up-count because of Q74=0, Q77=0, and Q75=0. When a broadcast is received in a frequency (fi), the F/F circuit 35 is reset because of Q74=1, Q77=1, and Q75=1, and the count of the counter 31 is stopped to set the receiving state. In this case, Q74 becomes 1 only when a broadcast is received to lock a PLL60 in a signal S55. Since the capture range of the PLL is generally about + or -100Hz, the error of the receiving frequency is within a range of + or -100Hz.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18320780A JPS57106217A (en) | 1980-12-24 | 1980-12-24 | Receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18320780A JPS57106217A (en) | 1980-12-24 | 1980-12-24 | Receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57106217A true JPS57106217A (en) | 1982-07-02 |
JPS6324568B2 JPS6324568B2 (en) | 1988-05-21 |
Family
ID=16131646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18320780A Granted JPS57106217A (en) | 1980-12-24 | 1980-12-24 | Receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57106217A (en) |
-
1980
- 1980-12-24 JP JP18320780A patent/JPS57106217A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6324568B2 (en) | 1988-05-21 |
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