JPS57101946A - Instruction storage device - Google Patents
Instruction storage deviceInfo
- Publication number
- JPS57101946A JPS57101946A JP55177292A JP17729280A JPS57101946A JP S57101946 A JPS57101946 A JP S57101946A JP 55177292 A JP55177292 A JP 55177292A JP 17729280 A JP17729280 A JP 17729280A JP S57101946 A JPS57101946 A JP S57101946A
- Authority
- JP
- Japan
- Prior art keywords
- data
- micro
- instruction
- exclusive
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE:To decrease the number of bits per 1 micro-instruction remarkably, by analyzing the working status of a micro-instruction, and constituting 2 micro- instructions containing an unused field, of 1 control storage word. CONSTITUTION:A read-out data D1 contains 2 micro-instructions MI-1, MI-2, and is constituted of CM for designating the constitution of MI-1, exclusive data F1-B1 of MI-1, exclusive data F2-TS2 of MI-2, and data U-X being common to both of them. Exclusive data of both MI-1 and MI-2 are selected by a switching circuit and are set to a register 52. Also, common data to 2 MIs and all ''0'' data which have set all bits to ''0'' are selected by switching circuits 53, 54, and the respective outputs are set to registers 55, 56. By the data of these registers 52, 55 and 56, a data D2 is formed, and it is set to an instruction register 6 as a micro-instruction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55177292A JPS57101946A (en) | 1980-12-17 | 1980-12-17 | Instruction storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55177292A JPS57101946A (en) | 1980-12-17 | 1980-12-17 | Instruction storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57101946A true JPS57101946A (en) | 1982-06-24 |
JPS6131893B2 JPS6131893B2 (en) | 1986-07-23 |
Family
ID=16028465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55177292A Granted JPS57101946A (en) | 1980-12-17 | 1980-12-17 | Instruction storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57101946A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6709818B2 (en) | 2018-03-29 | 2020-06-17 | 矢崎総業株式会社 | Wire with terminal |
JP2019175726A (en) | 2018-03-29 | 2019-10-10 | 矢崎総業株式会社 | Electric wire with terminal |
-
1980
- 1980-12-17 JP JP55177292A patent/JPS57101946A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6131893B2 (en) | 1986-07-23 |
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