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JPS5699540A - Graphic arithmetic circuit - Google Patents

Graphic arithmetic circuit

Info

Publication number
JPS5699540A
JPS5699540A JP118680A JP118680A JPS5699540A JP S5699540 A JPS5699540 A JP S5699540A JP 118680 A JP118680 A JP 118680A JP 118680 A JP118680 A JP 118680A JP S5699540 A JPS5699540 A JP S5699540A
Authority
JP
Japan
Prior art keywords
circuit
ordinate
result
contents
sent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP118680A
Other languages
Japanese (ja)
Inventor
Tomoki Shiyudo
Nobumasa Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP118680A priority Critical patent/JPS5699540A/en
Publication of JPS5699540A publication Critical patent/JPS5699540A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To calculate at a high speed the co-ordinate of a point which has been nested (n) times, by providing (n) pairs of co-ordinate registers for storing the X and Y co-ordinates, and a means for adding all the value of co-ordinates and adding said result and the input co-ordinate value.
CONSTITUTION: When a copying arrangement data corresponding to nesting of the graphic form is sent to the graphic arithmetic circuit from the electronic computer, it is stored in the co-ordinate registers 10W12. The contents of the register 10 and the co-ordinate data which is sent from the signal line 101 are added by the adder circuit 13, and its result is sent to the adder circuit 14. The circuit 14 addes the result of the circuit 13 and the contents of the register 11, and sends its result to the adder circuit 15. The circuit 15 adds the result of the circuit 14 and the contents of the register 12, and sends its result to the graphic form generating circuit through the signal line 102. The contents of the registers 10W12 are made x1Wx3, and when "x" has been sent to the signal line 101, x+x1+x2+x3 is output to the signal line 102. Since the co-ordinate of the copying arrangement graphic form which has been nested (n) times is calculated by a hardware, it is calculated at a high speed.
COPYRIGHT: (C)1981,JPO&Japio
JP118680A 1980-01-09 1980-01-09 Graphic arithmetic circuit Pending JPS5699540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP118680A JPS5699540A (en) 1980-01-09 1980-01-09 Graphic arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP118680A JPS5699540A (en) 1980-01-09 1980-01-09 Graphic arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS5699540A true JPS5699540A (en) 1981-08-10

Family

ID=11494413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP118680A Pending JPS5699540A (en) 1980-01-09 1980-01-09 Graphic arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS5699540A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294491A (en) * 1985-06-21 1986-12-25 株式会社　写研 Display data memory system for input editor
JPS61295596A (en) * 1985-06-25 1986-12-26 株式会社　写研 Data editing system for input editor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294491A (en) * 1985-06-21 1986-12-25 株式会社　写研 Display data memory system for input editor
JPS61295596A (en) * 1985-06-25 1986-12-26 株式会社　写研 Data editing system for input editor

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