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JPS5697173A - Operation processing system by mask - Google Patents

Operation processing system by mask

Info

Publication number
JPS5697173A
JPS5697173A JP17232179A JP17232179A JPS5697173A JP S5697173 A JPS5697173 A JP S5697173A JP 17232179 A JP17232179 A JP 17232179A JP 17232179 A JP17232179 A JP 17232179A JP S5697173 A JPS5697173 A JP S5697173A
Authority
JP
Japan
Prior art keywords
mask
operator
register
input
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17232179A
Other languages
Japanese (ja)
Inventor
Hideo Miyanaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17232179A priority Critical patent/JPS5697173A/en
Publication of JPS5697173A publication Critical patent/JPS5697173A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To reduce the number of times of operand readout, by controlling the execution of operation by a mask and enabling to indicate the types of operation and delivered customer. CONSTITUTION:When a vector operation is made and the multiplexer 11 selects the mask register, the operand data of vector register is read out one by one and input to the operator 5, and the mask information word is read out one by one from the mask register 4 and input to the operator 5. The operator 5 processes the input operand data in the mode that indicated in the mask information word. When the multiplexer 11 selects the output from the instruction control section 6, the execution indicating information is fed from the register 4 to the operator 4, and the operation type designation information and delivered customer designation information are fed from the control section 6. Thus, the number of times of operand read-in is reduced and the processing efficiency of computer can remarkably be increased.
JP17232179A 1979-12-29 1979-12-29 Operation processing system by mask Pending JPS5697173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17232179A JPS5697173A (en) 1979-12-29 1979-12-29 Operation processing system by mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17232179A JPS5697173A (en) 1979-12-29 1979-12-29 Operation processing system by mask

Publications (1)

Publication Number Publication Date
JPS5697173A true JPS5697173A (en) 1981-08-05

Family

ID=15939739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17232179A Pending JPS5697173A (en) 1979-12-29 1979-12-29 Operation processing system by mask

Country Status (1)

Country Link
JP (1) JPS5697173A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207967A (en) * 1984-03-31 1985-10-19 Toshiba Corp Vector arithmetic processor
JPS60251470A (en) * 1984-05-28 1985-12-12 Fujitsu Ltd Vector data processor
JPS61160176A (en) * 1984-12-29 1986-07-19 Hitachi Ltd Vector processing device
JPS623371A (en) * 1985-06-28 1987-01-09 Nec Corp Vector data processor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60207967A (en) * 1984-03-31 1985-10-19 Toshiba Corp Vector arithmetic processor
JPS60251470A (en) * 1984-05-28 1985-12-12 Fujitsu Ltd Vector data processor
JPS61160176A (en) * 1984-12-29 1986-07-19 Hitachi Ltd Vector processing device
JPS623371A (en) * 1985-06-28 1987-01-09 Nec Corp Vector data processor

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