[go: up one dir, main page]

JPS5693433A - Mos inverter circuit - Google Patents

Mos inverter circuit

Info

Publication number
JPS5693433A
JPS5693433A JP17369879A JP17369879A JPS5693433A JP S5693433 A JPS5693433 A JP S5693433A JP 17369879 A JP17369879 A JP 17369879A JP 17369879 A JP17369879 A JP 17369879A JP S5693433 A JPS5693433 A JP S5693433A
Authority
JP
Japan
Prior art keywords
level
input
fet3
turned
capacities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17369879A
Other languages
Japanese (ja)
Inventor
Hideyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17369879A priority Critical patent/JPS5693433A/en
Publication of JPS5693433A publication Critical patent/JPS5693433A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a quicker rise characteristic without increment of current consumption and the pattern area, by separating floating capacities of the output line by the transistor for capacity separation. CONSTITUTION:When the L-level input signal is input to input terminal 1, driver MOSFET3 and capacity separating MOSFET9 are turned off. Then, floating capacities 8 and 11 are separated completely. When the H-level input signal is input to input terminal 1, FET3 and FET9 are turned on. Electric charge of capacities 8 and 11 is discharged through turned-on FET3. Consequently, the level of terminal 13 becomes the L level determined by the resistance ratio among load MOSFET5, load MOSFET12 for pull-up, and FET3.
JP17369879A 1979-12-26 1979-12-26 Mos inverter circuit Pending JPS5693433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17369879A JPS5693433A (en) 1979-12-26 1979-12-26 Mos inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17369879A JPS5693433A (en) 1979-12-26 1979-12-26 Mos inverter circuit

Publications (1)

Publication Number Publication Date
JPS5693433A true JPS5693433A (en) 1981-07-29

Family

ID=15965453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17369879A Pending JPS5693433A (en) 1979-12-26 1979-12-26 Mos inverter circuit

Country Status (1)

Country Link
JP (1) JPS5693433A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628218A (en) * 1982-02-03 1986-12-09 Nippon Electric Co., Ltd. Driving circuit suppressing peak value of charging current from power supply to capacitive load

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628218A (en) * 1982-02-03 1986-12-09 Nippon Electric Co., Ltd. Driving circuit suppressing peak value of charging current from power supply to capacitive load

Similar Documents

Publication Publication Date Title
EP0093803A3 (en) Indicating system
JPS577632A (en) Electronic switch
JPS5693433A (en) Mos inverter circuit
JPS57152218A (en) Frequency and voltage converting circuit
JPS5783922A (en) Delay circuit
JPS5694856A (en) Stereo multiplex circuit
JPS57202118A (en) Chopper type mos comparator
JPS5710534A (en) High-voltage mos inverter and its driving method
JPS56100514A (en) Delay circuit
JPS57110076A (en) Booster circuit
JPS5693188A (en) Transfer pulse control system of charge transfer element
JPS56123127A (en) Logic circuit
JPS54105583A (en) Peak detection circuit
JPS57137875A (en) Terminal circuit
JPS5693185A (en) Transfer pulse control system of charge transfer element
JPS554110A (en) Control system
JPS5612562A (en) Circuit for discriminating connection state of terminal
JPS641327A (en) Or circuit device
JPS5673921A (en) Chattering rejection circuit
JPS5691536A (en) Multiple-valued level output circuit
JPS641326A (en) And circuit device
JPS57181229A (en) Driving circuit
JPS5611680A (en) Semiconductor memory
JPS56168433A (en) Charge pump circuit
JPS6481415A (en) Logic circuit