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JPS5690344A - Multiplication control system - Google Patents

Multiplication control system

Info

Publication number
JPS5690344A
JPS5690344A JP16776379A JP16776379A JPS5690344A JP S5690344 A JPS5690344 A JP S5690344A JP 16776379 A JP16776379 A JP 16776379A JP 16776379 A JP16776379 A JP 16776379A JP S5690344 A JPS5690344 A JP S5690344A
Authority
JP
Japan
Prior art keywords
register
data
selector
output
multiplicand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16776379A
Other languages
Japanese (ja)
Inventor
Haruhisa Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16776379A priority Critical patent/JPS5690344A/en
Publication of JPS5690344A publication Critical patent/JPS5690344A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To remarkably reduce the ratio of pre-processing to the repeat operation step, by selectively sending to an adder circuit the multiple value of the multiplicand generated by a bit shift, or the multiple value of the multiplicand which cannot be obtained by the bit shift.
CONSTITUTION: The multiplier MPR which has been input to the data line 201 is set to the register 102. At the same time, the 2MCD data which has shifted the multiplicand MCD which has been input to the data line 202, to the left by 1 bit is output from the selector 106, also the MCD data is output from the selector 107, and both of them are sent to the adder circuit 104 and are added. This added data is set to the register 103. Subsequently, the contents of the register 101 and the multiple value selected from the MCD which has been output from the selector 10 are added or subtracted. And, the data output by the circuit 104 is retained in the register 101 in the form of shifting to the right by 3 bits. Also, the low rank 3 bits of the circuits 104, which have been input from the selector 105 are coupled with the high rank of data of the register 102, and are stored in the register 102.
COPYRIGHT: (C)1981,JPO&Japio
JP16776379A 1979-12-24 1979-12-24 Multiplication control system Pending JPS5690344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16776379A JPS5690344A (en) 1979-12-24 1979-12-24 Multiplication control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16776379A JPS5690344A (en) 1979-12-24 1979-12-24 Multiplication control system

Publications (1)

Publication Number Publication Date
JPS5690344A true JPS5690344A (en) 1981-07-22

Family

ID=15855637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16776379A Pending JPS5690344A (en) 1979-12-24 1979-12-24 Multiplication control system

Country Status (1)

Country Link
JP (1) JPS5690344A (en)

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