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JPS5679303A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS5679303A
JPS5679303A JP15426979A JP15426979A JPS5679303A JP S5679303 A JPS5679303 A JP S5679303A JP 15426979 A JP15426979 A JP 15426979A JP 15426979 A JP15426979 A JP 15426979A JP S5679303 A JPS5679303 A JP S5679303A
Authority
JP
Japan
Prior art keywords
sequence
buffer memory
process input
data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15426979A
Other languages
Japanese (ja)
Inventor
Shigeru Chida
Kazuyoshi Asada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15426979A priority Critical patent/JPS5679303A/en
Publication of JPS5679303A publication Critical patent/JPS5679303A/en
Pending legal-status Critical Current

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  • Control By Computers (AREA)

Abstract

PURPOSE: To obtain a sequencer of high sequence control precision by eliminating the unsettled time of the rise of a plant process input for exhibiting sequence functions through data processing.
CONSTITUTION: The buffer memory consists of the 1st buffer memory stored with input-output data buffered in advance and the 2nd buffer memory stored with data buffered this time. Then, the RAM type buffer memory in process input-output device 3 is provided a data state change detecting mechanism, whose detection result is sent out via the data bus (DB) line to start the sequence data processing of processor 2. As a result, the sequence function is exhibited synchronizing with a change in process input and output, so that the unsettled time from the process input until the exhibtion of the sequencer function will be eliminated. Thus, the sequence of high sequence control precision can be obtained.
COPYRIGHT: (C)1981,JPO&Japio
JP15426979A 1979-11-30 1979-11-30 Sequence controller Pending JPS5679303A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15426979A JPS5679303A (en) 1979-11-30 1979-11-30 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15426979A JPS5679303A (en) 1979-11-30 1979-11-30 Sequence controller

Publications (1)

Publication Number Publication Date
JPS5679303A true JPS5679303A (en) 1981-06-29

Family

ID=15580468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15426979A Pending JPS5679303A (en) 1979-11-30 1979-11-30 Sequence controller

Country Status (1)

Country Link
JP (1) JPS5679303A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966722A (en) * 1982-10-08 1984-04-16 Hitachi Ltd Digital thyristor control system
WO1985004496A1 (en) * 1984-03-22 1985-10-10 Fanuc Ltd Analog input control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966722A (en) * 1982-10-08 1984-04-16 Hitachi Ltd Digital thyristor control system
JPH05725B2 (en) * 1982-10-08 1993-01-06 Hitachi Ltd
WO1985004496A1 (en) * 1984-03-22 1985-10-10 Fanuc Ltd Analog input control system

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