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JPS5674899A - Memory information protecting circuit - Google Patents

Memory information protecting circuit

Info

Publication number
JPS5674899A
JPS5674899A JP15092579A JP15092579A JPS5674899A JP S5674899 A JPS5674899 A JP S5674899A JP 15092579 A JP15092579 A JP 15092579A JP 15092579 A JP15092579 A JP 15092579A JP S5674899 A JPS5674899 A JP S5674899A
Authority
JP
Japan
Prior art keywords
flag
data
cell group
famos
eprom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15092579A
Other languages
Japanese (ja)
Other versions
JPS6128144B2 (en
Inventor
Isato Kazama
Hideharu Toyomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15092579A priority Critical patent/JPS5674899A/en
Publication of JPS5674899A publication Critical patent/JPS5674899A/en
Publication of JPS6128144B2 publication Critical patent/JPS6128144B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Read Only Memory (AREA)
  • Storage Device Security (AREA)

Abstract

PURPOSE:To retain secrecy by utilizing the fact that the EPROM (erasable ROM) cell of FAMOS (floating gate avalanche injection MOS circuit) construction is of a ultraviolet ray erasing type, so that make reading of stored data from the outside impossible. CONSTITUTION:Flag 3 composed of an EPROM cell of FAMOS construction is installed separately from EPROM cell group 1 of FAMOS construction. When flag 3 is under erased condition, data written on FAMOS cell group 1 can be read from output line 7. Moreover, when the write signal is given to flag 3 from write line 4 and flag 3 is set under the writing condition, reading of data of EPROM cell group 1 is prohibited and the data are not transmitted to output line 7. To read out the data from the outside, flag 3 must be set to an erased condition. If an ultraviolet ray is irradiated for this purpose, all pieces of information in EPROM cell group 1 which are the original data, are erased at the same time. Thus, secrecy information stored in cell group 1 is retained.
JP15092579A 1979-11-20 1979-11-20 Memory information protecting circuit Granted JPS5674899A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15092579A JPS5674899A (en) 1979-11-20 1979-11-20 Memory information protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15092579A JPS5674899A (en) 1979-11-20 1979-11-20 Memory information protecting circuit

Publications (2)

Publication Number Publication Date
JPS5674899A true JPS5674899A (en) 1981-06-20
JPS6128144B2 JPS6128144B2 (en) 1986-06-28

Family

ID=15507398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15092579A Granted JPS5674899A (en) 1979-11-20 1979-11-20 Memory information protecting circuit

Country Status (1)

Country Link
JP (1) JPS5674899A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5699945U (en) * 1979-12-27 1981-08-06
JPS5823398A (en) * 1981-08-04 1983-02-12 Fujitsu Ltd Microcomputer with memory content protective
JPS5894195A (en) * 1981-11-30 1983-06-04 Nec Home Electronics Ltd One chip microcomputer
JPH0455961A (en) * 1990-06-25 1992-02-24 Sigma Corp Microcomputer
JPH0476749A (en) * 1990-07-19 1992-03-11 Toshiba Corp Security circuit
JPH0520204A (en) * 1991-07-11 1993-01-29 Matsushita Electric Ind Co Ltd Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5699945U (en) * 1979-12-27 1981-08-06
JPS5823398A (en) * 1981-08-04 1983-02-12 Fujitsu Ltd Microcomputer with memory content protective
JPS5894195A (en) * 1981-11-30 1983-06-04 Nec Home Electronics Ltd One chip microcomputer
JPH0455961A (en) * 1990-06-25 1992-02-24 Sigma Corp Microcomputer
JPH0476749A (en) * 1990-07-19 1992-03-11 Toshiba Corp Security circuit
JPH0520204A (en) * 1991-07-11 1993-01-29 Matsushita Electric Ind Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS6128144B2 (en) 1986-06-28

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