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JPS5665547A - Self-synchronizing system - Google Patents

Self-synchronizing system

Info

Publication number
JPS5665547A
JPS5665547A JP14041879A JP14041879A JPS5665547A JP S5665547 A JPS5665547 A JP S5665547A JP 14041879 A JP14041879 A JP 14041879A JP 14041879 A JP14041879 A JP 14041879A JP S5665547 A JPS5665547 A JP S5665547A
Authority
JP
Japan
Prior art keywords
self
internal clock
counter
synchronizing signal
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14041879A
Other languages
Japanese (ja)
Inventor
Hideshi Kenjo
Masaharu Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP14041879A priority Critical patent/JPS5665547A/en
Publication of JPS5665547A publication Critical patent/JPS5665547A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To realize the self synchronizing system in which the state of synchronism is stably kept and quick return is made if out of synchronism is caused, in the self- synchronizing system of digital communication. CONSTITUTION:The output of a self-synchronizing signal generating circuit 2 in which the 1st internal clock is counted at the 1st counter and generated, and the output of a data bit synchronizing signal generating circuit 1 are compared, and the phase difference, lead and lag phase are detected 4, and the 1st internal clock is counted at the 2nd counter 5 at the period of phase difference. In case of delay phase, the 2nd internal clock higher than the 1st internal clock corresponding to the count value of the 2nd counter 5 is added to the 1st internal clock to correct the self- synchronizing signal, and in case of lead phase, the input of the 1st counter of the 1st internal clock is stopped by the number corresponding to the count value of the 2nd counter 5 to correct the self-synchronizing signal.
JP14041879A 1979-11-01 1979-11-01 Self-synchronizing system Pending JPS5665547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14041879A JPS5665547A (en) 1979-11-01 1979-11-01 Self-synchronizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14041879A JPS5665547A (en) 1979-11-01 1979-11-01 Self-synchronizing system

Publications (1)

Publication Number Publication Date
JPS5665547A true JPS5665547A (en) 1981-06-03

Family

ID=15268248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14041879A Pending JPS5665547A (en) 1979-11-01 1979-11-01 Self-synchronizing system

Country Status (1)

Country Link
JP (1) JPS5665547A (en)

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