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JPS566534A - Level converting circuit - Google Patents

Level converting circuit

Info

Publication number
JPS566534A
JPS566534A JP8135179A JP8135179A JPS566534A JP S566534 A JPS566534 A JP S566534A JP 8135179 A JP8135179 A JP 8135179A JP 8135179 A JP8135179 A JP 8135179A JP S566534 A JPS566534 A JP S566534A
Authority
JP
Japan
Prior art keywords
level
transistor
current
output
converting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8135179A
Other languages
Japanese (ja)
Inventor
Koji Masuda
Masao Mizukami
Nobuaki Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP8135179A priority Critical patent/JPS566534A/en
Priority to US06/157,853 priority patent/US4356409A/en
Priority to DE19803024274 priority patent/DE3024274A1/en
Publication of JPS566534A publication Critical patent/JPS566534A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the undesired level output by setting the output level of the level converting circuit forcedly to the level of one side when the power voltage becomes to the prescribed level or less. CONSTITUTION:When negative power voltage VEE becomes to a small voltage level in terms of the absolute value, no sufficient bias current is supplied to transistor Q10 at bias part 3. And thus the emitter current of Q10 is reduced, and accordingly the collector current is reduced for the collector of constant current transistor Q15 at level converting part 1. And the low-level potential of node N1 increases. Thus transistors Q18 and Q19 start conduction in case transistor Q13 is turned on by the emitter-coupled logic signal of input A. Then the level of output terminal P2 is turned forcedly to a low level.
JP8135179A 1979-06-29 1979-06-29 Level converting circuit Pending JPS566534A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8135179A JPS566534A (en) 1979-06-29 1979-06-29 Level converting circuit
US06/157,853 US4356409A (en) 1979-06-29 1980-06-09 Level conversion circuit
DE19803024274 DE3024274A1 (en) 1979-06-29 1980-06-27 LEVEL CONVERTER CONTROL

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8135179A JPS566534A (en) 1979-06-29 1979-06-29 Level converting circuit

Publications (1)

Publication Number Publication Date
JPS566534A true JPS566534A (en) 1981-01-23

Family

ID=13743938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8135179A Pending JPS566534A (en) 1979-06-29 1979-06-29 Level converting circuit

Country Status (1)

Country Link
JP (1) JPS566534A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5975720A (en) * 1982-10-25 1984-04-28 Seiko Instr & Electronics Ltd Semiconductor device
JPS6096600A (en) * 1983-10-28 1985-05-30 Toshiba Corp Lithium tantalate single crystal
JPS6157120A (en) * 1984-08-29 1986-03-24 Fujitsu Ltd TTL circuit with protection circuit
JPH03183677A (en) * 1980-10-02 1991-08-09 Xerox Corp Formation of electro-optical guided wave layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112530A (en) * 1973-02-23 1974-10-26
JPS51120143A (en) * 1975-03-26 1976-10-21 Honeywell Inf Systems Logical level translator
JPS54945A (en) * 1977-06-06 1979-01-06 Nec Corp Integrated circuit providing output control function

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112530A (en) * 1973-02-23 1974-10-26
JPS51120143A (en) * 1975-03-26 1976-10-21 Honeywell Inf Systems Logical level translator
JPS54945A (en) * 1977-06-06 1979-01-06 Nec Corp Integrated circuit providing output control function

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03183677A (en) * 1980-10-02 1991-08-09 Xerox Corp Formation of electro-optical guided wave layer
JPS5975720A (en) * 1982-10-25 1984-04-28 Seiko Instr & Electronics Ltd Semiconductor device
JPS6096600A (en) * 1983-10-28 1985-05-30 Toshiba Corp Lithium tantalate single crystal
JPS6157120A (en) * 1984-08-29 1986-03-24 Fujitsu Ltd TTL circuit with protection circuit

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