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JPS5650446A - Microcomputer test device - Google Patents

Microcomputer test device

Info

Publication number
JPS5650446A
JPS5650446A JP12499679A JP12499679A JPS5650446A JP S5650446 A JPS5650446 A JP S5650446A JP 12499679 A JP12499679 A JP 12499679A JP 12499679 A JP12499679 A JP 12499679A JP S5650446 A JPS5650446 A JP S5650446A
Authority
JP
Japan
Prior art keywords
section
program
memory
execution
tested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12499679A
Other languages
Japanese (ja)
Inventor
Hajime Kurii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12499679A priority Critical patent/JPS5650446A/en
Publication of JPS5650446A publication Critical patent/JPS5650446A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE: To store and display the execution log efficiently, by connecting a test device to the microcomputer to be tested to write and read programs and by stopping execution by detection of destruction of contents of the RAM or an arbitrary address of the program.
CONSTITUTION: The (μ)processor PU1 of micro(μ)computer TC to be tested is connected to (μ)computer test unit MDS, and the processing of processor PU1 executed by the same (μ)processor PU2 in device MDS. The program to be tested is stored in the first memory MU1 constituted in the RAM, and this memory MU1 is provided with the first section MU11 of the same word length as memory MU0 and the second section MU12 of a proper word length. Decode circuit TCF is connected to section MU12, and the operation start or stop request signal is sent to trace memory TRCM, and the program execution stop request signal is sent to execution control circuit STSC, and test information read from section MU12 is sent to circuit TCF, and control for program test is performed there.
COPYRIGHT: (C)1981,JPO&Japio
JP12499679A 1979-09-28 1979-09-28 Microcomputer test device Pending JPS5650446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12499679A JPS5650446A (en) 1979-09-28 1979-09-28 Microcomputer test device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12499679A JPS5650446A (en) 1979-09-28 1979-09-28 Microcomputer test device

Publications (1)

Publication Number Publication Date
JPS5650446A true JPS5650446A (en) 1981-05-07

Family

ID=14899302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12499679A Pending JPS5650446A (en) 1979-09-28 1979-09-28 Microcomputer test device

Country Status (1)

Country Link
JP (1) JPS5650446A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875254A (en) * 1981-10-28 1983-05-06 Nec Corp One-chip microcomputer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875254A (en) * 1981-10-28 1983-05-06 Nec Corp One-chip microcomputer system
JPS6212542B2 (en) * 1981-10-28 1987-03-19 Nippon Electric Co

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