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JPS5644953A - Parallel processor system - Google Patents

Parallel processor system

Info

Publication number
JPS5644953A
JPS5644953A JP12030179A JP12030179A JPS5644953A JP S5644953 A JPS5644953 A JP S5644953A JP 12030179 A JP12030179 A JP 12030179A JP 12030179 A JP12030179 A JP 12030179A JP S5644953 A JPS5644953 A JP S5644953A
Authority
JP
Japan
Prior art keywords
switch
instruction
processors
processor
memory modules
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12030179A
Other languages
Japanese (ja)
Inventor
Takenori Makino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12030179A priority Critical patent/JPS5644953A/en
Publication of JPS5644953A publication Critical patent/JPS5644953A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To reduce the number of switch control lines in comparison with the cross point switch to facilitate integration, by limiting connection between processors and memory modules while referring to memories.
CONSTITUTION: Control processor (CP) 3 sends the instruction, which processors (PE) should execute, to n-sets of PE 20W2n-1 through transfer line 135, and n-sets of PEs perform processings according to this instruction. When the instruction sent to PE 20W2n-1 has a read or write instruction to a memory, CP 3 controls S' switch 4, R' switch 5, R switch 6, and S' switch 7 through transfer lines 131W134. Thus, in case that the first processor among processors 20W2n-1 accesses address A+K.i (A and K are constants, i=0, 1, 2...n-1), connection between the processor and memory modules is given by Amod(m) and Kmod(m) (m is the number of memory modules), thus reducing the number of switch control lines to facilitate integration.
COPYRIGHT: (C)1981,JPO&Japio
JP12030179A 1979-09-18 1979-09-18 Parallel processor system Pending JPS5644953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12030179A JPS5644953A (en) 1979-09-18 1979-09-18 Parallel processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12030179A JPS5644953A (en) 1979-09-18 1979-09-18 Parallel processor system

Publications (1)

Publication Number Publication Date
JPS5644953A true JPS5644953A (en) 1981-04-24

Family

ID=14782841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12030179A Pending JPS5644953A (en) 1979-09-18 1979-09-18 Parallel processor system

Country Status (1)

Country Link
JP (1) JPS5644953A (en)

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