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JPS5640939A - Command flag control circuit - Google Patents

Command flag control circuit

Info

Publication number
JPS5640939A
JPS5640939A JP11554279A JP11554279A JPS5640939A JP S5640939 A JPS5640939 A JP S5640939A JP 11554279 A JP11554279 A JP 11554279A JP 11554279 A JP11554279 A JP 11554279A JP S5640939 A JPS5640939 A JP S5640939A
Authority
JP
Japan
Prior art keywords
command flag
decoder
output
address
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11554279A
Other languages
Japanese (ja)
Inventor
Seishi Kinoshita
Takatoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11554279A priority Critical patent/JPS5640939A/en
Publication of JPS5640939A publication Critical patent/JPS5640939A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure an independent control for the command flag of each control subject, by holding the status signal in the specified command flag by the output of the decoder designating the command flag plus the strobe signal supplied from the arithmetic control unit.
CONSTITUTION: The address decoder 22 decodes the higher-rank 6 bits of the I/O address given from the CPU21 and then detects the designation of the command flag 28. And the decoder 24 decodes the lower-rank 2 bits of the I/O address and then specifies one of the command flags 281W284. Both the output of the decoder 22 and the strobe signal of the CPU21 pass through the gate 25 to be applied to the AND gates 261W264. The output of the decoder 24 is applied to the other input of the gates 261W264 each. Thus the specified gate delivers the signal to set the corresponding flip-flops 281W284 and then holds the status signal.
COPYRIGHT: (C)1981,JPO&Japio
JP11554279A 1979-09-08 1979-09-08 Command flag control circuit Pending JPS5640939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11554279A JPS5640939A (en) 1979-09-08 1979-09-08 Command flag control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11554279A JPS5640939A (en) 1979-09-08 1979-09-08 Command flag control circuit

Publications (1)

Publication Number Publication Date
JPS5640939A true JPS5640939A (en) 1981-04-17

Family

ID=14665105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11554279A Pending JPS5640939A (en) 1979-09-08 1979-09-08 Command flag control circuit

Country Status (1)

Country Link
JP (1) JPS5640939A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110950U (en) * 1983-01-17 1984-07-26 伊勢電子工業株式会社 fluorescent display tube
JPS60184255U (en) * 1984-05-17 1985-12-06 伊勢電子工業株式会社 fluorescent display tube
JPH0390348U (en) * 1989-12-26 1991-09-13

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59110950U (en) * 1983-01-17 1984-07-26 伊勢電子工業株式会社 fluorescent display tube
JPS60184255U (en) * 1984-05-17 1985-12-06 伊勢電子工業株式会社 fluorescent display tube
JPH0215247Y2 (en) * 1984-05-17 1990-04-24
JPH0390348U (en) * 1989-12-26 1991-09-13
JP2526047Y2 (en) * 1989-12-26 1997-02-12 横河電機株式会社 Bus slave device

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