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JPS5633878A - Charge coupling type semiconductor memory device - Google Patents

Charge coupling type semiconductor memory device

Info

Publication number
JPS5633878A
JPS5633878A JP10915279A JP10915279A JPS5633878A JP S5633878 A JPS5633878 A JP S5633878A JP 10915279 A JP10915279 A JP 10915279A JP 10915279 A JP10915279 A JP 10915279A JP S5633878 A JPS5633878 A JP S5633878A
Authority
JP
Japan
Prior art keywords
channel region
register
memory device
type semiconductor
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10915279A
Other languages
Japanese (ja)
Inventor
Fumiaki Fujii
Takashi Oba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10915279A priority Critical patent/JPS5633878A/en
Publication of JPS5633878A publication Critical patent/JPS5633878A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/891—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D44/00, e.g. integration of charge-coupled devices [CCD] or charge injection devices [CID

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To reduce the number of cross wirings by a method wherein the latter half fortion of register is folded approximately in parallel to the former half portion, the charge input portion and the charge output portion are arranged in the same side of the register transfer portion. CONSTITUTION:The register is composed of a channel region CH1, a channel region CH2 connected to the channel region CH1 in the lower part, and a channel region CH3 which is arranged in parallel to the channel region CH1 and connected to the channel region CH2. Further, since the register is constituted is that the former half portion and the latter half portion are folded, the charge input portion 1 and the charge output portion 2 are arranged only at the one side of the register.
JP10915279A 1979-08-29 1979-08-29 Charge coupling type semiconductor memory device Pending JPS5633878A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10915279A JPS5633878A (en) 1979-08-29 1979-08-29 Charge coupling type semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10915279A JPS5633878A (en) 1979-08-29 1979-08-29 Charge coupling type semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5633878A true JPS5633878A (en) 1981-04-04

Family

ID=14502935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10915279A Pending JPS5633878A (en) 1979-08-29 1979-08-29 Charge coupling type semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5633878A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750949A (en) * 1984-11-10 1988-06-14 Nippon Steel Corporation Grain-oriented electrical steel sheet having stable magnetic properties resistant to stress-relief annealing, and method and apparatus for producing the same
JP2011258906A (en) * 2010-06-10 2011-12-22 Kinki Univ Ultrahigh-speed imaging element having signal integration function in element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750949A (en) * 1984-11-10 1988-06-14 Nippon Steel Corporation Grain-oriented electrical steel sheet having stable magnetic properties resistant to stress-relief annealing, and method and apparatus for producing the same
JP2011258906A (en) * 2010-06-10 2011-12-22 Kinki Univ Ultrahigh-speed imaging element having signal integration function in element

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