[go: up one dir, main page]

JPS5629757A - Analyzer for logic function working - Google Patents

Analyzer for logic function working

Info

Publication number
JPS5629757A
JPS5629757A JP10652779A JP10652779A JPS5629757A JP S5629757 A JPS5629757 A JP S5629757A JP 10652779 A JP10652779 A JP 10652779A JP 10652779 A JP10652779 A JP 10652779A JP S5629757 A JPS5629757 A JP S5629757A
Authority
JP
Japan
Prior art keywords
arithmetic
diagnosis
subject unit
computer
control part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10652779A
Other languages
Japanese (ja)
Other versions
JPS6230458B2 (en
Inventor
Takao Ichiko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10652779A priority Critical patent/JPS5629757A/en
Publication of JPS5629757A publication Critical patent/JPS5629757A/en
Publication of JPS6230458B2 publication Critical patent/JPS6230458B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To obtain the optimum design information of the subject unit for the logic function working analyzer which performs the monitor, diagnosis and working analysis each of a digital electronic computer, by having a dynamic execution for the logic of the subject unit with a proper monitor and diagnosis given to the subject unit.
CONSTITUTION: The main memory device 3 extracts and then stores the status of a number of logic circuit terminals in the subject digital electronic computer 1 and via the interface control part 2. The time control part 4 connected to the part 2 illustrates the time of the computer 1, and the state of the logic circuit at the time specified through the part 4 is sent to the arithmetic collating circuit 5 for an arithmetic collation with reception of the take-in bit pattern of the device 3. The result of the arithmetic collation is sent to the matrix information control part 6, and the input information is edited at the part 6. And the output of the part 6 is supplied to the device 3 to be stored, and at the same time the contents of storage is utilized when necessary. As a result, a proper monitor and diagnosis are carried out for computer 1, thus obtaining the optimum design information of the subject unit.
COPYRIGHT: (C)1981,JPO&Japio
JP10652779A 1979-08-20 1979-08-20 Analyzer for logic function working Granted JPS5629757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10652779A JPS5629757A (en) 1979-08-20 1979-08-20 Analyzer for logic function working

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10652779A JPS5629757A (en) 1979-08-20 1979-08-20 Analyzer for logic function working

Publications (2)

Publication Number Publication Date
JPS5629757A true JPS5629757A (en) 1981-03-25
JPS6230458B2 JPS6230458B2 (en) 1987-07-02

Family

ID=14435860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10652779A Granted JPS5629757A (en) 1979-08-20 1979-08-20 Analyzer for logic function working

Country Status (1)

Country Link
JP (1) JPS5629757A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4937827A (en) * 1985-03-01 1990-06-26 Mentor Graphics Corporation Circuit verification accessory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4937827A (en) * 1985-03-01 1990-06-26 Mentor Graphics Corporation Circuit verification accessory

Also Published As

Publication number Publication date
JPS6230458B2 (en) 1987-07-02

Similar Documents

Publication Publication Date Title
EP0111053A3 (en) On-chip monitor
JPS5585265A (en) Function test evaluation device for integrated circuit
JPS5629757A (en) Analyzer for logic function working
JPS5487130A (en) Conventional register access system
JPS56111961A (en) Data file control device
JPS5710846A (en) Information processing equipment
JPS5572261A (en) Logic unit
JPS55105722A (en) Initial program load system
JPS5674666A (en) Voltage level generator
JPS55159257A (en) Debugging system
JPS5547547A (en) Control device
JPS5549761A (en) Logical operation circuit testing unit
JPS57203162A (en) One-chip microcomputer
JPS5469044A (en) Input/output control system for lsi
JPS5694449A (en) Trace system in computer
EP0369407A3 (en) Central processing unit for data processor having emulation function
JPS5611369A (en) Diagnostic system of lsi
Kaiser Flexible logic enables new approach to tester design
JPS5453234A (en) Transmission fault processor controller
JPS5674761A (en) Information processor
JPS5674751A (en) Test system
JPS5476037A (en) Pla logic circuit
JPS5682960A (en) Bus control system
JPS5665253A (en) Debug device
JPS5671106A (en) Sequence control device