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JPS5619593A - Parity check processing system for memory - Google Patents

Parity check processing system for memory

Info

Publication number
JPS5619593A
JPS5619593A JP9343479A JP9343479A JPS5619593A JP S5619593 A JPS5619593 A JP S5619593A JP 9343479 A JP9343479 A JP 9343479A JP 9343479 A JP9343479 A JP 9343479A JP S5619593 A JPS5619593 A JP S5619593A
Authority
JP
Japan
Prior art keywords
area
block
memory
data
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9343479A
Other languages
Japanese (ja)
Inventor
Motoharu Asano
Hideo Matsuda
Yutaka Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9343479A priority Critical patent/JPS5619593A/en
Publication of JPS5619593A publication Critical patent/JPS5619593A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To perform different parity check according to the importance of data, by sectioning the memory area into a plurality of blocks and providing respectively the parity addition and check circuit.
CONSTITUTION: The memory area of the main memory 2 is sectioned into the block 1 of the area 21 and the block 2 of the area 22, and the data less important is stored to the area 21 and the data of high importance is stored to the area 22 respectively. Further, the block 1 is provided with the parity addition and check circuit 23 having the function of error detection and the block 2 is provided with the parity addition and check circuit 24 having error detection and corrective function. Thus, the result of check of the circuits 23, 24 is respectively reported separately on the status display register 3, then the processor 1 makes different processing depending on the importance of the stored data based on the content of the register 3.
COPYRIGHT: (C)1981,JPO&Japio
JP9343479A 1979-07-23 1979-07-23 Parity check processing system for memory Pending JPS5619593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9343479A JPS5619593A (en) 1979-07-23 1979-07-23 Parity check processing system for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9343479A JPS5619593A (en) 1979-07-23 1979-07-23 Parity check processing system for memory

Publications (1)

Publication Number Publication Date
JPS5619593A true JPS5619593A (en) 1981-02-24

Family

ID=14082195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9343479A Pending JPS5619593A (en) 1979-07-23 1979-07-23 Parity check processing system for memory

Country Status (1)

Country Link
JP (1) JPS5619593A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4032571A1 (en) * 1989-10-16 1991-05-02 Ibm DEVICE FOR THE TREATMENT OF PARITY ERRORS IN STORAGE GROUPS OF PERSONNEL COMPUTERS
US5177747A (en) * 1989-10-16 1993-01-05 International Business Machines Corp. Personal computer memory bank parity error indicator
EP0645773A1 (en) * 1993-09-29 1995-03-29 France Telecom Procedure to update a memory card and memory implementing this procedure
US6782492B1 (en) 1998-05-11 2004-08-24 Nec Corporation Memory error recovery method in a cluster computer and a cluster computer
US8341503B1 (en) * 2006-11-30 2012-12-25 Marvell International Ltd. Methods and systems for storing data in memory using zoning
JP2016066236A (en) * 2014-09-25 2016-04-28 日立オートモティブシステムズ株式会社 Built-in control device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4032571A1 (en) * 1989-10-16 1991-05-02 Ibm DEVICE FOR THE TREATMENT OF PARITY ERRORS IN STORAGE GROUPS OF PERSONNEL COMPUTERS
JPH03132829A (en) * 1989-10-16 1991-06-06 Internatl Business Mach Corp <Ibm> Parity inspection system
US5177747A (en) * 1989-10-16 1993-01-05 International Business Machines Corp. Personal computer memory bank parity error indicator
EP0645773A1 (en) * 1993-09-29 1995-03-29 France Telecom Procedure to update a memory card and memory implementing this procedure
FR2710775A1 (en) * 1993-09-29 1995-04-07 France Telecom Method for updating a memory and memory card using this method.
US6782492B1 (en) 1998-05-11 2004-08-24 Nec Corporation Memory error recovery method in a cluster computer and a cluster computer
US8341503B1 (en) * 2006-11-30 2012-12-25 Marvell International Ltd. Methods and systems for storing data in memory using zoning
US8799724B1 (en) 2006-11-30 2014-08-05 Marvell International Ltd. Methods and systems for storing data in memory using zoning
JP2016066236A (en) * 2014-09-25 2016-04-28 日立オートモティブシステムズ株式会社 Built-in control device

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