JPS56168268A - Logical circuit having diagnosis clock - Google Patents
Logical circuit having diagnosis clockInfo
- Publication number
- JPS56168268A JPS56168268A JP7223980A JP7223980A JPS56168268A JP S56168268 A JPS56168268 A JP S56168268A JP 7223980 A JP7223980 A JP 7223980A JP 7223980 A JP7223980 A JP 7223980A JP S56168268 A JPS56168268 A JP S56168268A
- Authority
- JP
- Japan
- Prior art keywords
- state
- diagnosis
- scan
- diagnosis clock
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To diagnose asynchronous operations by the use of a scan-in/scan-out technique by providing plural diagnosis clock signals which do not overlap each other, and gating the asynchronous input signal of a state storage circuit with one diagnosis clock signal. CONSTITUTION:Pulses are applied to a diagnosis clock DCK 1 without applying clock inputs. Thereafter, both diagnosis clock inputs are set at a ''0'' and scan-out is carried out by shifting whereby the state of an FF35 is checked. If the state of the FF33 has changed in the expected state ''1'' of a signal line 48, it is ckecked that the state of the signal line 48 is correct and that a gate 60 and the AI input of the FF33 are normal. If the state of the FF33 does not change, it indicates that the state of the signal line 48 is ''0'', or that there is a ''0'' fault in the gate 60 or that there is a ''0'' fault in the AI input of the FF33. Arrangement is so made that the state change of the FF33 is not propagated to an adjacent FF32.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7223980A JPS56168268A (en) | 1980-05-30 | 1980-05-30 | Logical circuit having diagnosis clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7223980A JPS56168268A (en) | 1980-05-30 | 1980-05-30 | Logical circuit having diagnosis clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56168268A true JPS56168268A (en) | 1981-12-24 |
Family
ID=13483531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7223980A Pending JPS56168268A (en) | 1980-05-30 | 1980-05-30 | Logical circuit having diagnosis clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56168268A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902856B2 (en) | 2009-02-16 | 2011-03-08 | Renesas Electronics Corporation | Semiconductor integrated circuit |
-
1980
- 1980-05-30 JP JP7223980A patent/JPS56168268A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902856B2 (en) | 2009-02-16 | 2011-03-08 | Renesas Electronics Corporation | Semiconductor integrated circuit |
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