JPS56166564A - Access system of main storage device - Google Patents
Access system of main storage deviceInfo
- Publication number
- JPS56166564A JPS56166564A JP6859080A JP6859080A JPS56166564A JP S56166564 A JPS56166564 A JP S56166564A JP 6859080 A JP6859080 A JP 6859080A JP 6859080 A JP6859080 A JP 6859080A JP S56166564 A JPS56166564 A JP S56166564A
- Authority
- JP
- Japan
- Prior art keywords
- main storage
- storage device
- data
- read
- significant bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Abstract
PURPOSE:To execute a diagnosis or the like of main storage device except existing machines, by designating a main storage device to be read in, in case of reading the data from main storage device in which the same data are simultaneously written in the same address. CONSTITUTION:The written-in data are simultaneously stored in the same address designated by the address information other than the most significant bit of the storage section of both the main storage devices MM0 and MM1. On the other hand, the read out data is read, out from only the storage section in the main storage device MM0 if the most significant bit of the address information is 0 and from only the main storage device if the bit is 1. Thus, a central control device CC0 can read in data from the main storage device MM0 or MM1 by instructing the most significant bit of the address information to logical 1 or 0.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6859080A JPS56166564A (en) | 1980-05-23 | 1980-05-23 | Access system of main storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6859080A JPS56166564A (en) | 1980-05-23 | 1980-05-23 | Access system of main storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56166564A true JPS56166564A (en) | 1981-12-21 |
Family
ID=13378154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6859080A Pending JPS56166564A (en) | 1980-05-23 | 1980-05-23 | Access system of main storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56166564A (en) |
-
1980
- 1980-05-23 JP JP6859080A patent/JPS56166564A/en active Pending
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