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JPS56164550A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56164550A
JPS56164550A JP6736280A JP6736280A JPS56164550A JP S56164550 A JPS56164550 A JP S56164550A JP 6736280 A JP6736280 A JP 6736280A JP 6736280 A JP6736280 A JP 6736280A JP S56164550 A JPS56164550 A JP S56164550A
Authority
JP
Japan
Prior art keywords
film
nitride
oxide
opening section
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6736280A
Other languages
Japanese (ja)
Other versions
JPS6322065B2 (en
Inventor
Yunosuke Kawabe
Yoshinobu Monma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6736280A priority Critical patent/JPS56164550A/en
Publication of JPS56164550A publication Critical patent/JPS56164550A/en
Publication of JPS6322065B2 publication Critical patent/JPS6322065B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent the occurrence of birdbeak and to increase the integration of a circuit by arranging a second Si nitride filn at the side of a two-layer film opening section consisting of an Si oxide film and an Si nitride film wherein the insulating film constitution is consisted as a selective oxide mask. CONSTITUTION:An opening section 5 is formed at a two-layer film isolation region between elements consisting of an oxide film 2 and a nitride film 3 provided on an Si substrate 1. Next, after piling the second nitride film 6 on the whole surface of the film 3, ion implantation is applied so that B may be implanted into only the film 6, for example. Next, the whole surface of the film 6 is etched by using the characteristic of quick etching speed for the nitride film implanted ion and films 6' thickly formed at the side of the opening section are left. Then, the films 2, 3, 6' are consisted as masks to form an isolation oxide layer 7 by selective oxidization. In this way, the occurrence of birdbeak can be prevented as oxidization through the film 2 is checked and the integration of each kind of integrated circuit can be improved.
JP6736280A 1980-05-21 1980-05-21 Manufacture of semiconductor device Granted JPS56164550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6736280A JPS56164550A (en) 1980-05-21 1980-05-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6736280A JPS56164550A (en) 1980-05-21 1980-05-21 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS56164550A true JPS56164550A (en) 1981-12-17
JPS6322065B2 JPS6322065B2 (en) 1988-05-10

Family

ID=13342821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6736280A Granted JPS56164550A (en) 1980-05-21 1980-05-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56164550A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61270846A (en) * 1985-05-24 1986-12-01 Matsushita Electronics Corp Semiconductor device
JPS6415946A (en) * 1987-07-10 1989-01-19 Hitachi Ltd Manufacture of semiconductor device
US5173444A (en) * 1990-09-18 1992-12-22 Sharp Kabushiki Kaisha Method for forming a semiconductor device isolation region

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165637A (en) * 1979-06-11 1980-12-24 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165637A (en) * 1979-06-11 1980-12-24 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61270846A (en) * 1985-05-24 1986-12-01 Matsushita Electronics Corp Semiconductor device
JPS6415946A (en) * 1987-07-10 1989-01-19 Hitachi Ltd Manufacture of semiconductor device
US5173444A (en) * 1990-09-18 1992-12-22 Sharp Kabushiki Kaisha Method for forming a semiconductor device isolation region

Also Published As

Publication number Publication date
JPS6322065B2 (en) 1988-05-10

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