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JPS56162529A - Voltage comparison circuit - Google Patents

Voltage comparison circuit

Info

Publication number
JPS56162529A
JPS56162529A JP6667380A JP6667380A JPS56162529A JP S56162529 A JPS56162529 A JP S56162529A JP 6667380 A JP6667380 A JP 6667380A JP 6667380 A JP6667380 A JP 6667380A JP S56162529 A JPS56162529 A JP S56162529A
Authority
JP
Japan
Prior art keywords
voltage
power consumption
load circuit
fets
fluctuations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6667380A
Other languages
Japanese (ja)
Inventor
Tojiro Takegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6667380A priority Critical patent/JPS56162529A/en
Publication of JPS56162529A publication Critical patent/JPS56162529A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve precision and to reduce power consumption considerably by holding a gate voltage of depletion type FET forming load circuit, and by absorbing fluctuations of a power voltage by those FETs. CONSTITUTION:Corresponding to the logical inversion of control signals S1 and S2, a voltage at an input terminal IN is compared. At this time, a low-level signal is supplied as a control signal S3 and a transistor (TR)Q12 is on. Therefore, the integrating circuit composed of a TRQ11 and a capacitor C3 operates and its time constant is greater than the inversion period of the signals S1 and S2. Consequently, even if a power voltage VD fluctuates, gate voltages of depletion FETs Q5-Q8 forming a load circuit are held constant, so the fluctuations are absorbed by the TRQ5-Q8, generating no comparison error. Thus, the precision is improved and the power consumption is reduced considerably.
JP6667380A 1980-05-20 1980-05-20 Voltage comparison circuit Pending JPS56162529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6667380A JPS56162529A (en) 1980-05-20 1980-05-20 Voltage comparison circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6667380A JPS56162529A (en) 1980-05-20 1980-05-20 Voltage comparison circuit

Publications (1)

Publication Number Publication Date
JPS56162529A true JPS56162529A (en) 1981-12-14

Family

ID=13322663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6667380A Pending JPS56162529A (en) 1980-05-20 1980-05-20 Voltage comparison circuit

Country Status (1)

Country Link
JP (1) JPS56162529A (en)

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