JPS56159726A - Bus request processor - Google Patents

Abstract

PURPOSE:To control a bus request signal and bus acknowledgment signal in terms of both priority and timing by providing each equipment with a bus request processor supplied with the bus acknowledgment signal and by determining the conditions of the use of a common bus by the request processor. CONSTITUTION:Control lines 8a-8d are signal lines which send bus request signals to a CPU1, and control lines 9a-9d are signal lines which send bus acknowledgment signals from the CPU1 to equipments 7a-7c. The control lines 8a-8c are connected to inputs of a bus request processor 10 in parallel, and the control line 8d transfers one bus request signal to the CPU1. The control line 9d sends the bus acknowledgment signal from the CPU1 to the bus request processor 10, and the control lines 9a-9c send bus acknowledgment signals to equipments 7a-7c, respectively. In this case, only one of the control lines 9a-9c, determined by the bus request processor 10, sends the bus acknowledgment signal actually.