JPS56157541A - Pseudo and multi central processor - Google Patents

Abstract

PURPOSE:To improve the execution efficiency, by providing a general-purpose register, a program counter, and plural register groups which indicate internal states of status flags, etc. and by executing programs assigned to register groups in time division. CONSTITUTION:A general-purpose register, a program counter, and register groups 1a-1n which indicate internal states of status flags, etc. are provided in the pseudo and multi processor 6, and these register groups 1a-1n are connected to a change- over switch part 2. Further, an arithmetic part 3 is connected to the change-over switch part 2, and a peripheral device 4 including a main memory and a group designating part 5 which instructs the connection the change-over switch part 2 are connected to this arithmetic part 3. When the arithmetic part 3 fetches and executes instructions in addresses of connected register groups 1a-1n, a designating part 5 receives the operation end signal from the arithmetic part 3, and the connection of the switch part 2 is switched to connect new register groups 1a-1n, and thus, programs assigned to register groups 1a-1n are executed in time division.