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JPS56153579A - Semiconductor storage circuit - Google Patents

Semiconductor storage circuit

Info

Publication number
JPS56153579A
JPS56153579A JP5739280A JP5739280A JPS56153579A JP S56153579 A JPS56153579 A JP S56153579A JP 5739280 A JP5739280 A JP 5739280A JP 5739280 A JP5739280 A JP 5739280A JP S56153579 A JPS56153579 A JP S56153579A
Authority
JP
Japan
Prior art keywords
potential
transistor
charge
conducts
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5739280A
Other languages
Japanese (ja)
Inventor
Zensuke Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5739280A priority Critical patent/JPS56153579A/en
Publication of JPS56153579A publication Critical patent/JPS56153579A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To enable the amplification of a differential signal with stability and good reproducibility, by charging two capacitive elements into high potential for one and low potential for another with FET respectively, and obtaning the intermediate potential by conducting between the capacitive elements being finished charge. CONSTITUTION:The signal phig conducts the transistor TR' to charge the capacitor CR' at low potential and conducts the transistor TR'' to charge the capacitor CR'' at high potential. Next, the signal phis conducts the transistor TS to charge the potential of the capacitors CR', CR'' at an intermediate value between the high and low poentials. After that, by conducting the transistor TS, it is equivalent for the dummy cell DC' that it is constituted with the capacitor having equal capacitance as the memory cell. Thus, the dummy cell DC' less in the effect of variance is established and the amplificaton of the differential signal with stability and good reproducibility is achieved.
JP5739280A 1980-04-30 1980-04-30 Semiconductor storage circuit Pending JPS56153579A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5739280A JPS56153579A (en) 1980-04-30 1980-04-30 Semiconductor storage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5739280A JPS56153579A (en) 1980-04-30 1980-04-30 Semiconductor storage circuit

Publications (1)

Publication Number Publication Date
JPS56153579A true JPS56153579A (en) 1981-11-27

Family

ID=13054337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5739280A Pending JPS56153579A (en) 1980-04-30 1980-04-30 Semiconductor storage circuit

Country Status (1)

Country Link
JP (1) JPS56153579A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182191A (en) * 1982-04-19 1983-10-25 Oki Electric Ind Co Ltd Storage device
JPS6187300A (en) * 1984-10-05 1986-05-02 Nec Corp Semiconductor memory
JPH0624781U (en) * 1992-09-04 1994-04-05 有限会社松阪精電舎 Product cleaning equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427734A (en) * 1977-08-03 1979-03-02 Toshiba Corp Dynamic semiconductor memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427734A (en) * 1977-08-03 1979-03-02 Toshiba Corp Dynamic semiconductor memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182191A (en) * 1982-04-19 1983-10-25 Oki Electric Ind Co Ltd Storage device
JPS6187300A (en) * 1984-10-05 1986-05-02 Nec Corp Semiconductor memory
JPH0624781U (en) * 1992-09-04 1994-04-05 有限会社松阪精電舎 Product cleaning equipment

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