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JPS56140429A - Advanced processing system for power supply abnormality in multiprocessor processing system - Google Patents

Advanced processing system for power supply abnormality in multiprocessor processing system

Info

Publication number
JPS56140429A
JPS56140429A JP4370780A JP4370780A JPS56140429A JP S56140429 A JPS56140429 A JP S56140429A JP 4370780 A JP4370780 A JP 4370780A JP 4370780 A JP4370780 A JP 4370780A JP S56140429 A JPS56140429 A JP S56140429A
Authority
JP
Japan
Prior art keywords
power supply
devices
processing system
cpus
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4370780A
Other languages
Japanese (ja)
Other versions
JPS5816483B2 (en
Inventor
Hiroshi Maruoka
Kunikazu Imai
Akihiko Suzuki
Hiroyuki Abiko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP55043707A priority Critical patent/JPS5816483B2/en
Publication of JPS56140429A publication Critical patent/JPS56140429A/en
Publication of JPS5816483B2 publication Critical patent/JPS5816483B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Multi Processors (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE:To restrain the influence upon processings of other systems to a minimum, by turning off the switching device of the system, where power supply abnormality occurs, in advance of the stored program control, in the system where plural CPUs use plural peripheral devices in common. CONSTITUTION:CPUs 1-1-1-3 and peripheral device systems 3-1-3-n are linked by turning on and off CPU busses 2-1-2-3 and peripheral device system busses 4-1-4-n through switching devices SW11-SW3n. Power is supplied to respective CPUs and peripheral devices by power supply devices 6-1-6-3 and 7-1-7-n. Configuration processing device 8 which performs the power supply control of systems in accordance with abnormality of power supply devices by the stored program control is provided with advanced processing part 9 and processor part 10. When abnormality occurs in a power supply device, processing part 9 performs the control to turn off the switching device related to the abnormal power supply without waiting the processing obtained by processor 10, and after that, processor part 10 reports the turning-off state of the switching device to CPUs through configuration control devices 5-1-5-3.
JP55043707A 1980-04-03 1980-04-03 Power failure advance processing method in multiprocessor processing systems Expired JPS5816483B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55043707A JPS5816483B2 (en) 1980-04-03 1980-04-03 Power failure advance processing method in multiprocessor processing systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55043707A JPS5816483B2 (en) 1980-04-03 1980-04-03 Power failure advance processing method in multiprocessor processing systems

Publications (2)

Publication Number Publication Date
JPS56140429A true JPS56140429A (en) 1981-11-02
JPS5816483B2 JPS5816483B2 (en) 1983-03-31

Family

ID=12671278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55043707A Expired JPS5816483B2 (en) 1980-04-03 1980-04-03 Power failure advance processing method in multiprocessor processing systems

Country Status (1)

Country Link
JP (1) JPS5816483B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024634A (en) * 1983-07-21 1985-02-07 Matsushita Electric Ind Co Ltd Digital signal processing device
KR100478478B1 (en) * 1998-09-11 2005-03-23 인텔 코오퍼레이션 A power failure safe computer architecture

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6141987U (en) * 1984-08-21 1986-03-18 トーセツ株式会社 Supply and exhaust pipes for combustion appliances

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024634A (en) * 1983-07-21 1985-02-07 Matsushita Electric Ind Co Ltd Digital signal processing device
KR100478478B1 (en) * 1998-09-11 2005-03-23 인텔 코오퍼레이션 A power failure safe computer architecture

Also Published As

Publication number Publication date
JPS5816483B2 (en) 1983-03-31

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