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JPS56137404A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS56137404A
JPS56137404A JP3893980A JP3893980A JPS56137404A JP S56137404 A JPS56137404 A JP S56137404A JP 3893980 A JP3893980 A JP 3893980A JP 3893980 A JP3893980 A JP 3893980A JP S56137404 A JPS56137404 A JP S56137404A
Authority
JP
Japan
Prior art keywords
section
input
output
instruction
storage section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3893980A
Other languages
Japanese (ja)
Inventor
Naohiro Kurokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3893980A priority Critical patent/JPS56137404A/en
Publication of JPS56137404A publication Critical patent/JPS56137404A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To enable to handle a number of input and output points, by providing the instruction deciding section and the operation processor at the program storage section, and restricting the increase in the number of steps accompanied with the increase in the number of output elements of the result and the number of logic input elements. CONSTITUTION:The signal input section 1 receiving the external input signal, output section 3, program input section 4, program storage section 5, and control section 2 are provided. Further, the storage section 5 arranges the presence of the selection in bit unit in response to a plurality of input/output terminals 11, 31 incorporated in the input/output section as the input/output element. Further, the control section 2 decides the instruction element in the storage section 5 at the instruction deciding section 22. The operation processor 21 makes operation based on the instruction signal from the instruction deciding section 22 with external input signal by separating the input set element in the storage section 5 into each bit or a plurality of groups, and controls the output section 3 based on the result of operation.
JP3893980A 1980-03-28 1980-03-28 Sequence controller Pending JPS56137404A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3893980A JPS56137404A (en) 1980-03-28 1980-03-28 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3893980A JPS56137404A (en) 1980-03-28 1980-03-28 Sequence controller

Publications (1)

Publication Number Publication Date
JPS56137404A true JPS56137404A (en) 1981-10-27

Family

ID=12539188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3893980A Pending JPS56137404A (en) 1980-03-28 1980-03-28 Sequence controller

Country Status (1)

Country Link
JP (1) JPS56137404A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58140849A (en) * 1982-02-17 1983-08-20 Hitachi Ltd programmable logic controller
JPS60155230U (en) * 1984-03-26 1985-10-16 オムロン株式会社 programmable counter device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58140849A (en) * 1982-02-17 1983-08-20 Hitachi Ltd programmable logic controller
JPH0561647B2 (en) * 1982-02-17 1993-09-06 Hitachi Ltd
JPS60155230U (en) * 1984-03-26 1985-10-16 オムロン株式会社 programmable counter device
JPH0426884Y2 (en) * 1984-03-26 1992-06-29

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