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JPS56136064A - Circuit monitor system - Google Patents

Circuit monitor system

Info

Publication number
JPS56136064A
JPS56136064A JP3903980A JP3903980A JPS56136064A JP S56136064 A JPS56136064 A JP S56136064A JP 3903980 A JP3903980 A JP 3903980A JP 3903980 A JP3903980 A JP 3903980A JP S56136064 A JPS56136064 A JP S56136064A
Authority
JP
Japan
Prior art keywords
circuit
data
contents
buffer
cpu8
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3903980A
Other languages
Japanese (ja)
Inventor
Chifuyu Saegusa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3903980A priority Critical patent/JPS56136064A/en
Publication of JPS56136064A publication Critical patent/JPS56136064A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To facilitate analysis of data without providing a circuit monitoring circuit by providing a log area for data received from a circuit in a memory, by dumping the contents of the log area when a fault occurs, and by finding the cause of a trouble on the basis of the dumped contents. CONSTITUTION:Data received from communication circuit 1 is converted from series to parallel by circuit control circuit 2 and on one-character reception, circuit 2 outputs interruption signal 7 to CPU8. On detecting this signal 7, CPU8 fetches the data and stores it in locking buffer 4 by way of data buffer 3 according to control program 5, and then data that CPU8 requires is stored in buffer 3. In the occurrence of the trouble, the contents of locking buffer 4 are dumped and on the basis of the dumped contents, the cause of the trouble is found, so that an analysis of data is easily made without using a complex device such as a circuit monitor.
JP3903980A 1980-03-28 1980-03-28 Circuit monitor system Pending JPS56136064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3903980A JPS56136064A (en) 1980-03-28 1980-03-28 Circuit monitor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3903980A JPS56136064A (en) 1980-03-28 1980-03-28 Circuit monitor system

Publications (1)

Publication Number Publication Date
JPS56136064A true JPS56136064A (en) 1981-10-23

Family

ID=12541971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3903980A Pending JPS56136064A (en) 1980-03-28 1980-03-28 Circuit monitor system

Country Status (1)

Country Link
JP (1) JPS56136064A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254945A (en) * 1984-05-31 1985-12-16 Fujitsu Ltd Logging control method of data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254945A (en) * 1984-05-31 1985-12-16 Fujitsu Ltd Logging control method of data processor

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