JPS56135962A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS56135962A JPS56135962A JP3989380A JP3989380A JPS56135962A JP S56135962 A JPS56135962 A JP S56135962A JP 3989380 A JP3989380 A JP 3989380A JP 3989380 A JP3989380 A JP 3989380A JP S56135962 A JPS56135962 A JP S56135962A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- forming
- lines
- digit lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To obtain a memory structure of large capacity by forming digit lines of the conductive 3rd wiring layer running on the 1st polycrystalline silicon layer, forming file address lines in the same layer and forming row address lines in an upper layer. CONSTITUTION:One-transistor one-capacitor type memory cell wherein a capacitor electrode is formed of the 1st polycrystalline silicon layer P1 and a gate electrode of MOS transistors Q1 and Q2 of the 2nd polycrystalline silicon layer P2 is provided and groups of the memory cells are arranged on both sides of a group of sense amplifiers. While the 1st polycrystalline layer P1 is made common to all the columns, the digit lines DG1, DG2 and the file address line CL are formed of the 3rd conductive wiring layer and the row address line RL is formed of the 4th wiring layer. Since the digit lines DG1, DG2 and the edges CE1, CE2 of the capacitors C1, C2 can be made to approach each other, the integration of high degree can be performed.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3989380A JPS56135962A (en) | 1980-03-28 | 1980-03-28 | Semiconductor memory device |
US06/245,728 US4384347A (en) | 1980-03-28 | 1981-03-20 | Semiconductor memory device |
DE8181301226T DE3172401D1 (en) | 1980-03-28 | 1981-03-23 | Semiconductor memory device |
EP81301226A EP0037227B1 (en) | 1980-03-28 | 1981-03-23 | Semiconductor memory device |
IE707/81A IE51238B1 (en) | 1980-03-28 | 1981-03-27 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3989380A JPS56135962A (en) | 1980-03-28 | 1980-03-28 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56135962A true JPS56135962A (en) | 1981-10-23 |
Family
ID=12565637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3989380A Pending JPS56135962A (en) | 1980-03-28 | 1980-03-28 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56135962A (en) |
-
1980
- 1980-03-28 JP JP3989380A patent/JPS56135962A/en active Pending
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