JPS56129448A - Failure detection method for signal transmitter and its device - Google Patents
Failure detection method for signal transmitter and its deviceInfo
- Publication number
- JPS56129448A JPS56129448A JP3278480A JP3278480A JPS56129448A JP S56129448 A JPS56129448 A JP S56129448A JP 3278480 A JP3278480 A JP 3278480A JP 3278480 A JP3278480 A JP 3278480A JP S56129448 A JPS56129448 A JP S56129448A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transmission
- check signal
- failure
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title 1
- 230000005540 biological transmission Effects 0.000 abstract 5
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000012544 monitoring process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Selective Calling Equipment (AREA)
Abstract
PURPOSE:To enable to discriminate the trouble of hardware if it is located at transmission or reception side, by transmitting the signal with check signal in which the state of signal is changed in a given period and monitoring this signal at transmission and reception ends. CONSTITUTION:At the transmission side, the check signal generator 4 produces the bit signal which is ON/OFF in a given period. This signal is added to the process signal group at the parallel-serial conversion circuit 5 and given on the transmission line 17 and also fed to the check signal monitor circuit 7. The monitor circuit 7 monitors the ON/OFF of check signal time to detect a failure. The check signal monitor circuit15 monitors the ON/OFF state of the check signal timewise at the reception side to detect the failure. Thus, it is accurately detected that the failure is brought out at transmission or reception side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3278480A JPS56129448A (en) | 1980-03-17 | 1980-03-17 | Failure detection method for signal transmitter and its device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3278480A JPS56129448A (en) | 1980-03-17 | 1980-03-17 | Failure detection method for signal transmitter and its device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56129448A true JPS56129448A (en) | 1981-10-09 |
Family
ID=12368471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3278480A Pending JPS56129448A (en) | 1980-03-17 | 1980-03-17 | Failure detection method for signal transmitter and its device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56129448A (en) |
-
1980
- 1980-03-17 JP JP3278480A patent/JPS56129448A/en active Pending
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