JPS56124952A - Information processing equipment - Google Patents
Information processing equipmentInfo
- Publication number
- JPS56124952A JPS56124952A JP2086480A JP2086480A JPS56124952A JP S56124952 A JPS56124952 A JP S56124952A JP 2086480 A JP2086480 A JP 2086480A JP 2086480 A JP2086480 A JP 2086480A JP S56124952 A JPS56124952 A JP S56124952A
- Authority
- JP
- Japan
- Prior art keywords
- specific instruction
- detected
- stored
- specific
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To execute a specific instruction without increasing a microprogram, by generating an interruption in the instruction executing procedure which has been stored in advance in a part of the main memory, when a specific instruction has been detected or when occuring of a specific event has been detected. CONSTITUTION:The main memory is logically divided into two, a memory address is assigned irrespectivey of its division, a regular software is stored in one divided area, a string of the specific instruction executing procedure is stored in the other divided area, and when a specific instruction is executed by the arithmetic unit or when a specific event has occurred, its state is detected and the gates 2, 3 are made on by the operand register. The FF 7 is set by outputs of said gates 2, 3, a hardware mode signal is made ''1'', and when the program interruption has occurred, a constant is input to the index register 5. Also, the contents of the boundary address are set to the base register 4, the contents of both the registers 4, 5 are added to the 3-input adder 6, and the executing procedure string of the specific instruction is accessed by a new address by the result of said addition.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2086480A JPS599937B2 (en) | 1980-02-20 | 1980-02-20 | information processing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2086480A JPS599937B2 (en) | 1980-02-20 | 1980-02-20 | information processing equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56124952A true JPS56124952A (en) | 1981-09-30 |
JPS599937B2 JPS599937B2 (en) | 1984-03-06 |
Family
ID=12039001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2086480A Expired JPS599937B2 (en) | 1980-02-20 | 1980-02-20 | information processing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS599937B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5971550A (en) * | 1982-09-30 | 1984-04-23 | Fujitsu Ltd | Instruction processing system |
JPS59200345A (en) * | 1983-04-26 | 1984-11-13 | Nec Corp | Microprogram control system |
JPS6083142A (en) * | 1983-10-14 | 1985-05-11 | Nec Corp | Microprogram controller |
JPS63173130A (en) * | 1986-12-30 | 1988-07-16 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Apparatus for expanding instruction set of computer |
JPH0331932A (en) * | 1989-06-28 | 1991-02-12 | Nec Corp | Data processor |
JPH05108488A (en) * | 1991-10-16 | 1993-04-30 | Fujitsu Ltd | System and device for controlling firmware program storing area |
JPH05233325A (en) * | 1991-08-30 | 1993-09-10 | Intel Corp | Microprocessor device and method for performing interrupts and automated I / O trap restart |
JPH05250183A (en) * | 1991-08-30 | 1993-09-28 | Intel Corp | Microprocessor device and CPU interrupt method |
-
1980
- 1980-02-20 JP JP2086480A patent/JPS599937B2/en not_active Expired
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5971550A (en) * | 1982-09-30 | 1984-04-23 | Fujitsu Ltd | Instruction processing system |
JPS59200345A (en) * | 1983-04-26 | 1984-11-13 | Nec Corp | Microprogram control system |
JPS6083142A (en) * | 1983-10-14 | 1985-05-11 | Nec Corp | Microprogram controller |
JPS63173130A (en) * | 1986-12-30 | 1988-07-16 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Apparatus for expanding instruction set of computer |
JPH0331932A (en) * | 1989-06-28 | 1991-02-12 | Nec Corp | Data processor |
JPH05233325A (en) * | 1991-08-30 | 1993-09-10 | Intel Corp | Microprocessor device and method for performing interrupts and automated I / O trap restart |
JPH05250183A (en) * | 1991-08-30 | 1993-09-28 | Intel Corp | Microprocessor device and CPU interrupt method |
JPH05108488A (en) * | 1991-10-16 | 1993-04-30 | Fujitsu Ltd | System and device for controlling firmware program storing area |
Also Published As
Publication number | Publication date |
---|---|
JPS599937B2 (en) | 1984-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5576447A (en) | Address control system for software simulation | |
JPS55112651A (en) | Virtual computer system | |
HK66884A (en) | Instruction set modifier register | |
KR860004355A (en) | Processor capable of running one or several programs on multiple calculations | |
EP0264216A3 (en) | Implied domain addressing | |
JPS56124952A (en) | Information processing equipment | |
US4460970A (en) | Digital data processing system using unique techniques for handling the leading digits and the signs of operands in arithmetic operations | |
GB1464570A (en) | Microprogramme control units | |
GB1537429A (en) | Text processing system | |
JPS5739457A (en) | Program device | |
EP0301707A3 (en) | Apparatus and method for providing an extended processing environment on nonmicrocoded data processing system | |
JP2557629B2 (en) | Interrupt method | |
JPS57203279A (en) | Information processing device | |
KR890002759A (en) | Device for modifying data element and method | |
JPS56147246A (en) | Program control device | |
JPS5757349A (en) | Microprogram control type data processor | |
EP0264215A3 (en) | Fast entry to emulation | |
JPS5447455A (en) | Data processor | |
Burke et al. | Emulating a Honeywell 6180 Computer System | |
JPS569841A (en) | Operation system of working register | |
SU411450A1 (en) | ||
JPS57755A (en) | Information processor | |
JPS57176455A (en) | Microprogram control information processor | |
JPS57132255A (en) | Program tracing system | |
JPS5467348A (en) | Microprogram control system |