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JPS56121152A - Monitor system of computer program - Google Patents

Monitor system of computer program

Info

Publication number
JPS56121152A
JPS56121152A JP2272680A JP2272680A JPS56121152A JP S56121152 A JPS56121152 A JP S56121152A JP 2272680 A JP2272680 A JP 2272680A JP 2272680 A JP2272680 A JP 2272680A JP S56121152 A JPS56121152 A JP S56121152A
Authority
JP
Japan
Prior art keywords
contents
transferred
memory
accumulator
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2272680A
Other languages
Japanese (ja)
Inventor
Tomokatsu Sato
Mitsuo Takakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2272680A priority Critical patent/JPS56121152A/en
Publication of JPS56121152A publication Critical patent/JPS56121152A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Programmable Controllers (AREA)
  • Detection And Correction Of Errors (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To easily generate, confirm and correct a program of the computer, by adding the information of 1 bit or more to an existing instruction, and discriminating a head word of the instruction or its nonhead word. CONSTITUTION:The contents of the memory 2 are transferred to the accumulator 4. In this case, the contents I1 of the instruction bit 1 are transferred to the auxiliary register 3. Subsequently, the contents D2 of the accumulator 4 are transferred to the control memory 8. Next, the contents I2 of the register I2 are transferred to the accumulator 4. Next, the contents I3 of the accumulator 4 are transferred to the memory 8. As a result, the contents of the memory 2 and the bit 1 can be stored in the memory 8. On the other hand, in case when a data which has been transmitted is written in the memory, the contents I1 of the memory 8 are transferred to the accumulator 4, and subsequently they are transferred to the register 3. Next, the data D1 of the memory 8 is transferred to the accumulator 4. After that, when the contents D2 of the accumulator 4 are transferred to the memory 2, the contents I3 of the register 3 are written in the bit 1.
JP2272680A 1980-02-27 1980-02-27 Monitor system of computer program Pending JPS56121152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2272680A JPS56121152A (en) 1980-02-27 1980-02-27 Monitor system of computer program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2272680A JPS56121152A (en) 1980-02-27 1980-02-27 Monitor system of computer program

Publications (1)

Publication Number Publication Date
JPS56121152A true JPS56121152A (en) 1981-09-22

Family

ID=12090758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2272680A Pending JPS56121152A (en) 1980-02-27 1980-02-27 Monitor system of computer program

Country Status (1)

Country Link
JP (1) JPS56121152A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5783807A (en) * 1980-11-14 1982-05-25 Omron Tateisi Electronics Co Programmable logic controller
JPS59206962A (en) * 1983-05-11 1984-11-22 Mitsubishi Electric Corp Data storage processing device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259537A (en) * 1975-11-11 1977-05-17 Mitsubishi Electric Corp Data processor
JPS5495144A (en) * 1978-01-13 1979-07-27 Hitachi Ltd Malfunction detection system in data processing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259537A (en) * 1975-11-11 1977-05-17 Mitsubishi Electric Corp Data processor
JPS5495144A (en) * 1978-01-13 1979-07-27 Hitachi Ltd Malfunction detection system in data processing unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5783807A (en) * 1980-11-14 1982-05-25 Omron Tateisi Electronics Co Programmable logic controller
JPS6116085B2 (en) * 1980-11-14 1986-04-28 Omron Tateisi Electronics Co
JPS59206962A (en) * 1983-05-11 1984-11-22 Mitsubishi Electric Corp Data storage processing device

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