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JPS56110169A - Multiprocessor processing system - Google Patents

Multiprocessor processing system

Info

Publication number
JPS56110169A
JPS56110169A JP1328180A JP1328180A JPS56110169A JP S56110169 A JPS56110169 A JP S56110169A JP 1328180 A JP1328180 A JP 1328180A JP 1328180 A JP1328180 A JP 1328180A JP S56110169 A JPS56110169 A JP S56110169A
Authority
JP
Japan
Prior art keywords
fifo
bus
processors
register groups
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1328180A
Other languages
Japanese (ja)
Other versions
JPS5835294B2 (en
Inventor
Takashi Nakamura
Yasuo Doi
Fumio Shimomura
Toshihiko Hiraide
Katsuteru Nagafuku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP55013281A priority Critical patent/JPS5835294B2/en
Publication of JPS56110169A publication Critical patent/JPS56110169A/en
Publication of JPS5835294B2 publication Critical patent/JPS5835294B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/067—Bidirectional FIFO, i.e. system allowing data transfer in two directions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To improve processing capacity by providing first-in first-out register groups storing data of predefined fixed lengths between respectively independent processors, and accumulating the processing requests between the processors into the register groups. CONSTITUTION:Plural processors PA, PB and storages MEM-A, MEM-B are connected to system buses BUS-A, BUS-B, whereby the multiprocessor processing system is constituted. First-in first-out register groups FIFO-1, FIFO-2 are connected via an interrupt control circuit INTC between these processors PA and PB, and the respective register groups FIFO-1, FIFO-2 are connected to the BUS-A, BUS-B. The processing requests from the respective processor PA or PB are written in the register group FIFO-1 or FIFO-2, and the respective processing requests are detected through the control circuit INTC, thereafter the contents of the processing requests are read into the processor PB or PA on the other side, whereby the processing capacity is improved.
JP55013281A 1980-02-06 1980-02-06 Multiprocessor processing method Expired JPS5835294B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55013281A JPS5835294B2 (en) 1980-02-06 1980-02-06 Multiprocessor processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55013281A JPS5835294B2 (en) 1980-02-06 1980-02-06 Multiprocessor processing method

Publications (2)

Publication Number Publication Date
JPS56110169A true JPS56110169A (en) 1981-09-01
JPS5835294B2 JPS5835294B2 (en) 1983-08-02

Family

ID=11828808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55013281A Expired JPS5835294B2 (en) 1980-02-06 1980-02-06 Multiprocessor processing method

Country Status (1)

Country Link
JP (1) JPS5835294B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2517442A1 (en) * 1981-12-02 1983-06-03 Western Electric Co INTERRUPTION DEVICE FOR MULTITRATING SYSTEM, METHOD FOR CONTROLLING THE SAME, AND SYSTEM FOR IMPLEMENTING SAME
JPS58203562A (en) * 1982-05-21 1983-11-28 Nec Corp Method for controlling memory
JPS59117619A (en) * 1982-12-24 1984-07-07 Omron Tateisi Electronics Co Data transfer processing device
JPS6444571A (en) * 1987-08-12 1989-02-16 Omron Tateisi Electronics Co Inter-processor coupling system
US4866597A (en) * 1984-04-26 1989-09-12 Kabushiki Kaisha Toshiba Multiprocessor system and control method therefor
JPH06162226A (en) * 1992-11-20 1994-06-10 Nec Corp Parallel processor controller

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6438798U (en) * 1987-09-03 1989-03-08
JPH01227396A (en) * 1988-03-05 1989-09-11 Stanley Electric Co Ltd Long-sized el element
JPH0322394U (en) * 1989-07-13 1991-03-07

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54103649A (en) * 1978-02-01 1979-08-15 Matsushita Electric Ind Co Ltd Data transmission control system between arithmetic control elements

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54103649A (en) * 1978-02-01 1979-08-15 Matsushita Electric Ind Co Ltd Data transmission control system between arithmetic control elements

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2517442A1 (en) * 1981-12-02 1983-06-03 Western Electric Co INTERRUPTION DEVICE FOR MULTITRATING SYSTEM, METHOD FOR CONTROLLING THE SAME, AND SYSTEM FOR IMPLEMENTING SAME
JPS58203562A (en) * 1982-05-21 1983-11-28 Nec Corp Method for controlling memory
JPS59117619A (en) * 1982-12-24 1984-07-07 Omron Tateisi Electronics Co Data transfer processing device
US4866597A (en) * 1984-04-26 1989-09-12 Kabushiki Kaisha Toshiba Multiprocessor system and control method therefor
JPS6444571A (en) * 1987-08-12 1989-02-16 Omron Tateisi Electronics Co Inter-processor coupling system
JPH06162226A (en) * 1992-11-20 1994-06-10 Nec Corp Parallel processor controller

Also Published As

Publication number Publication date
JPS5835294B2 (en) 1983-08-02

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