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JPS56104449A - Integrated circuit element - Google Patents

Integrated circuit element

Info

Publication number
JPS56104449A
JPS56104449A JP653380A JP653380A JPS56104449A JP S56104449 A JPS56104449 A JP S56104449A JP 653380 A JP653380 A JP 653380A JP 653380 A JP653380 A JP 653380A JP S56104449 A JPS56104449 A JP S56104449A
Authority
JP
Japan
Prior art keywords
memory
integrated circuit
bits
defect
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP653380A
Other languages
Japanese (ja)
Inventor
Hiroshi Egawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP653380A priority Critical patent/JPS56104449A/en
Publication of JPS56104449A publication Critical patent/JPS56104449A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the memory storage capacity of a defect register memory by corresponding the respective one bits of memory to predetermined switching blocks of the large-scale integrated circuit. CONSTITUTION:In the large-scale integrated circuit 7 in which basic elements 1-1- 1-4 and preliminary elements 1-5, 1-6 are connected through signal wire 2 to a signal terminal 3, a plurality of bits (indicated by lattice-shaped rectnagles) are formed in switching blocks, and defect information of the circuit 7 is stored in the defect register memory 4 formed by corresponding them to the respective one bits. An element 8 having a pair of the memory 4 and the circuit 7 is formed on a monocrystalline substrate. Thus, the storage capacity of the memory 4 can be reduced. Further, address conversion information is formed on the basis of the defect information to control the preliminary switching, thereby increasing the application to the system.
JP653380A 1980-01-23 1980-01-23 Integrated circuit element Pending JPS56104449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP653380A JPS56104449A (en) 1980-01-23 1980-01-23 Integrated circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP653380A JPS56104449A (en) 1980-01-23 1980-01-23 Integrated circuit element

Publications (1)

Publication Number Publication Date
JPS56104449A true JPS56104449A (en) 1981-08-20

Family

ID=11640988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP653380A Pending JPS56104449A (en) 1980-01-23 1980-01-23 Integrated circuit element

Country Status (1)

Country Link
JP (1) JPS56104449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217492A (en) * 1986-02-18 1987-09-24 Fujitsu Ltd Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62217492A (en) * 1986-02-18 1987-09-24 Fujitsu Ltd Semiconductor memory device

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