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JPS56101760A - Formation of package of semiconductors - Google Patents

Formation of package of semiconductors

Info

Publication number
JPS56101760A
JPS56101760A JP517680A JP517680A JPS56101760A JP S56101760 A JPS56101760 A JP S56101760A JP 517680 A JP517680 A JP 517680A JP 517680 A JP517680 A JP 517680A JP S56101760 A JPS56101760 A JP S56101760A
Authority
JP
Japan
Prior art keywords
molds
lead frame
integrating
recess
planar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP517680A
Other languages
Japanese (ja)
Other versions
JPS6138862B2 (en
Inventor
Keiji Hazama
Mitsuyoshi Nakatsuka
Shinichi Oota
Kiichi Kanamaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP517680A priority Critical patent/JPS56101760A/en
Publication of JPS56101760A publication Critical patent/JPS56101760A/en
Publication of JPS6138862B2 publication Critical patent/JPS6138862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To conduct an excellent sealing of the package of the semiconductors by heating two planar molded members having recess for containing a semiconductor by mating in integrating molds, then interposing a lead frame therebetween, pressing to mate them and thereby preventing the production of flash. CONSTITUTION:The lead frame 4 is interposed between the integrating molds 9 and 9', the planar molded member 3 is disposed in the recess 17 of the integrating molds 9 in the state that the mating surfaces 16 of the member 3 are brought into contact with the lead frame 4, a heater guide hole 19 passed through the recess 17' of the molds 9' is perforated on one side of the mold 9' in the state that the part 18 making contact with the lead frame is retained on the one side surface of the mold 9', the heater 20 is inserted from the hole 19, the planar molded momber 3' is so disposed as not to contact therewith, heated, and the heater 20 is removed, and then the members are confronted integrally and heated by planar molde member pressing machines 12, 12'. Since the peripheries of the planar molded members are completely closed in this manner, it can prevent the production of flash.
JP517680A 1980-01-18 1980-01-18 Formation of package of semiconductors Granted JPS56101760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP517680A JPS56101760A (en) 1980-01-18 1980-01-18 Formation of package of semiconductors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP517680A JPS56101760A (en) 1980-01-18 1980-01-18 Formation of package of semiconductors

Publications (2)

Publication Number Publication Date
JPS56101760A true JPS56101760A (en) 1981-08-14
JPS6138862B2 JPS6138862B2 (en) 1986-09-01

Family

ID=11603922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP517680A Granted JPS56101760A (en) 1980-01-18 1980-01-18 Formation of package of semiconductors

Country Status (1)

Country Link
JP (1) JPS56101760A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680617A (en) * 1984-05-23 1987-07-14 Ross Milton I Encapsulated electronic circuit device, and method and apparatus for making same
US4872825A (en) * 1984-05-23 1989-10-10 Ross Milton I Method and apparatus for making encapsulated electronic circuit devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680617A (en) * 1984-05-23 1987-07-14 Ross Milton I Encapsulated electronic circuit device, and method and apparatus for making same
US4872825A (en) * 1984-05-23 1989-10-10 Ross Milton I Method and apparatus for making encapsulated electronic circuit devices

Also Published As

Publication number Publication date
JPS6138862B2 (en) 1986-09-01

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