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JPS5596712A - Mounting system of electronic circuit - Google Patents

Mounting system of electronic circuit

Info

Publication number
JPS5596712A
JPS5596712A JP433379A JP433379A JPS5596712A JP S5596712 A JPS5596712 A JP S5596712A JP 433379 A JP433379 A JP 433379A JP 433379 A JP433379 A JP 433379A JP S5596712 A JPS5596712 A JP S5596712A
Authority
JP
Japan
Prior art keywords
interval
signal line
characteristic impedance
signal
capacities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP433379A
Other languages
Japanese (ja)
Inventor
Kazunori Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP433379A priority Critical patent/JPS5596712A/en
Publication of JPS5596712A publication Critical patent/JPS5596712A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P9/00—Delay lines of the waveguide type

Landscapes

  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make impedance uniform to reduce distortion of the waveform by fitting a capacitor to the wiring part, where no load is fitted, in the system where the delay time for propagation through wiring is longer in comparison with the rise and break time of signals. CONSTITUTION:Interval l of loads IC 1a-1f is shorter than distance t0/td where a signal is propagated through the signal line of propagation delay time td per unit length within rise and break time t0 of the signal. Interval l0 between driving IC 3 and load ICs is sufficiently longer than t0/td. In this circuit, the swaveform is distorted due to negative reflection of characteristic impedance Z3 of the signal line across capacities 6a-6f> characteristic impedance Z2 of the signal line across IC 1a-1i. Therefore, capacities 6a-6f are fitted at interval l1(l1<t0/td) to make characteristic impedance Z3 equal to Z2. Thus, a high-speed transmission circuit without delay loss can be realized.
JP433379A 1979-01-18 1979-01-18 Mounting system of electronic circuit Pending JPS5596712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP433379A JPS5596712A (en) 1979-01-18 1979-01-18 Mounting system of electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP433379A JPS5596712A (en) 1979-01-18 1979-01-18 Mounting system of electronic circuit

Publications (1)

Publication Number Publication Date
JPS5596712A true JPS5596712A (en) 1980-07-23

Family

ID=11581516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP433379A Pending JPS5596712A (en) 1979-01-18 1979-01-18 Mounting system of electronic circuit

Country Status (1)

Country Link
JP (1) JPS5596712A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63183680A (en) * 1987-01-26 1988-07-29 Hitachi Ltd semiconductor storage device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63183680A (en) * 1987-01-26 1988-07-29 Hitachi Ltd semiconductor storage device

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