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JPS5593350A - Clock reproduction unit - Google Patents

Clock reproduction unit

Info

Publication number
JPS5593350A
JPS5593350A JP143079A JP143079A JPS5593350A JP S5593350 A JPS5593350 A JP S5593350A JP 143079 A JP143079 A JP 143079A JP 143079 A JP143079 A JP 143079A JP S5593350 A JPS5593350 A JP S5593350A
Authority
JP
Japan
Prior art keywords
clock
reference clock
phase
picked
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP143079A
Other languages
Japanese (ja)
Inventor
Makoto Miyake
Hisashi Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP143079A priority Critical patent/JPS5593350A/en
Publication of JPS5593350A publication Critical patent/JPS5593350A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain stable clock similar to the picked up clock in phase based on the detected output, by detecting the phase difference between the clock picked up from the reception signal and the reference clock, in the digital communication such as time sharing multiplex connection. CONSTITUTION:The clock is picked up at the clock reproduction circuit 2 from the input from the reception signal input terminal 1. The picked up clock and the reference clock from the terminal 4 are inputted to the phase detector 5. The level of the phase detected output is judged at the level discriminator 8 and inputted to the switch 9. The reference clock is inputted to the switch 9 and the reference clock in 180 deg. phase shift is inputted to the switch circuit 9. Further, if the output of the level discriminator 8 is more than specified level, the reference clock is outputted to the terminal 11 as it is and if less than the specified level, the reference clock phase shifted by 180 deg. is outputted.
JP143079A 1979-01-08 1979-01-08 Clock reproduction unit Pending JPS5593350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP143079A JPS5593350A (en) 1979-01-08 1979-01-08 Clock reproduction unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP143079A JPS5593350A (en) 1979-01-08 1979-01-08 Clock reproduction unit

Publications (1)

Publication Number Publication Date
JPS5593350A true JPS5593350A (en) 1980-07-15

Family

ID=11501233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP143079A Pending JPS5593350A (en) 1979-01-08 1979-01-08 Clock reproduction unit

Country Status (1)

Country Link
JP (1) JPS5593350A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5761358A (en) * 1980-07-17 1982-04-13 Rockwell International Corp Digital signal synchronizing system
JPS58121851A (en) * 1982-01-14 1983-07-20 Canon Inc Synchronizing circuit
JPS6128251A (en) * 1984-07-19 1986-02-07 Nitsuko Ltd Clock synchronizing system
JPS61120538A (en) * 1984-11-15 1986-06-07 Nec Corp Multi-direction multiplex communication equipment
JPS6265535A (en) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> Clock asynchronizing data detection system
JPS6265536A (en) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> Clock asynchronizing data detection system
JPH02211735A (en) * 1989-02-10 1990-08-23 Matsushita Electric Ind Co Ltd Bit synchronizing device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5761358A (en) * 1980-07-17 1982-04-13 Rockwell International Corp Digital signal synchronizing system
JPS6255746B2 (en) * 1980-07-17 1987-11-20 Rockwell International Corp
JPS58121851A (en) * 1982-01-14 1983-07-20 Canon Inc Synchronizing circuit
JPS6128251A (en) * 1984-07-19 1986-02-07 Nitsuko Ltd Clock synchronizing system
JPH0584691B2 (en) * 1984-07-19 1993-12-02 Nitsuko Ltd
JPS61120538A (en) * 1984-11-15 1986-06-07 Nec Corp Multi-direction multiplex communication equipment
JPS6265535A (en) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> Clock asynchronizing data detection system
JPS6265536A (en) * 1985-09-17 1987-03-24 Nippon Telegr & Teleph Corp <Ntt> Clock asynchronizing data detection system
JPH02211735A (en) * 1989-02-10 1990-08-23 Matsushita Electric Ind Co Ltd Bit synchronizing device

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