JPS5592007A - Signal processing unit - Google Patents
Signal processing unitInfo
- Publication number
- JPS5592007A JPS5592007A JP16432078A JP16432078A JPS5592007A JP S5592007 A JPS5592007 A JP S5592007A JP 16432078 A JP16432078 A JP 16432078A JP 16432078 A JP16432078 A JP 16432078A JP S5592007 A JPS5592007 A JP S5592007A
- Authority
- JP
- Japan
- Prior art keywords
- deltae
- output signal
- sampling hold
- zero point
- subjected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 abstract 4
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
PURPOSE:To eliminate completely the influence of zero point fluctuation and slide by subjection the peak value and the zero point of a waveform signal, which is chopped by a chopper and is amplified, to sampling hold and by calculating difference of both signals by subtraction. CONSTITUTION:DC input signal e1 is chopped by chopper 2 which is driven by timing signal f0 of pulse generator 5, and amplified output signal e2 becomes a sinnal corresponding to Ae1+DELTAe where base fluctuation components DELTAe are su perposed. Voltage Ae1+DELTAe of the peak value of this output signal e2 is subjected to sampling hold by the first sample hold circuit 41. Voltage DELTAe of the zero point of output signal e2 is subjected to sampling hold by the second sample hold circuit 42. Difference between these signals subjected to sampling hold is calculated by subtractor 6, and a correct output signal is taken out from terminal 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16432078A JPS5592007A (en) | 1978-12-29 | 1978-12-29 | Signal processing unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16432078A JPS5592007A (en) | 1978-12-29 | 1978-12-29 | Signal processing unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5592007A true JPS5592007A (en) | 1980-07-12 |
Family
ID=15790903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16432078A Pending JPS5592007A (en) | 1978-12-29 | 1978-12-29 | Signal processing unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5592007A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101141567B1 (en) | 2006-02-07 | 2012-05-16 | 각코우호진 지코우지가쿠엔 | Amplifier circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4966262A (en) * | 1972-10-30 | 1974-06-27 | ||
JPS51120659A (en) * | 1975-04-15 | 1976-10-22 | Matsushita Electric Works Ltd | Dc amplifier circuit |
JPS5476051A (en) * | 1977-11-30 | 1979-06-18 | Matsushita Electric Ind Co Ltd | Bridge amplifier circuit |
-
1978
- 1978-12-29 JP JP16432078A patent/JPS5592007A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4966262A (en) * | 1972-10-30 | 1974-06-27 | ||
JPS51120659A (en) * | 1975-04-15 | 1976-10-22 | Matsushita Electric Works Ltd | Dc amplifier circuit |
JPS5476051A (en) * | 1977-11-30 | 1979-06-18 | Matsushita Electric Ind Co Ltd | Bridge amplifier circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101141567B1 (en) | 2006-02-07 | 2012-05-16 | 각코우호진 지코우지가쿠엔 | Amplifier circuit |
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