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JPS5569838A - Pattern data generator - Google Patents

Pattern data generator

Info

Publication number
JPS5569838A
JPS5569838A JP14328178A JP14328178A JPS5569838A JP S5569838 A JPS5569838 A JP S5569838A JP 14328178 A JP14328178 A JP 14328178A JP 14328178 A JP14328178 A JP 14328178A JP S5569838 A JPS5569838 A JP S5569838A
Authority
JP
Japan
Prior art keywords
block
character
pattern
data
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14328178A
Other languages
Japanese (ja)
Inventor
Nobuaki Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP14328178A priority Critical patent/JPS5569838A/en
Publication of JPS5569838A publication Critical patent/JPS5569838A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To represent a pattern for one character by a small number of bits by dividing the dot pattern for one character into several blocks and then by assigning short block codes according to appearance probability at the time or coding.
CONSTITUTION: Row and column addresses UA and LA of an assigned character are assigned and a block code is sent from block pattern memory part 1. Synchronizing with a read signal through gate 4, codes are read in sequence and converted into parallel data, which are sent to decoder 8. On detecting block data consisting of two bits when the content of block assignment counter 6 is "2", decoder 8 inhibits signal P and stops read operation. When the data is not detected, an advance is made and dot pattern memory part 9 reads a not pattern equivalent to decoded data and sends it to a display part after conversion 11 into series data synchronizing with load signal L, thereby clearing block assignment counter 6 by load signal L. This constitution expresses a pattern for one character by a small number of bits.
COPYRIGHT: (C)1980,JPO&Japio
JP14328178A 1978-11-22 1978-11-22 Pattern data generator Pending JPS5569838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14328178A JPS5569838A (en) 1978-11-22 1978-11-22 Pattern data generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14328178A JPS5569838A (en) 1978-11-22 1978-11-22 Pattern data generator

Publications (1)

Publication Number Publication Date
JPS5569838A true JPS5569838A (en) 1980-05-26

Family

ID=15335080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14328178A Pending JPS5569838A (en) 1978-11-22 1978-11-22 Pattern data generator

Country Status (1)

Country Link
JP (1) JPS5569838A (en)

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