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JPS5562725A - Method of forming narrow diffused region on silicon substrate - Google Patents

Method of forming narrow diffused region on silicon substrate

Info

Publication number
JPS5562725A
JPS5562725A JP13093979A JP13093979A JPS5562725A JP S5562725 A JPS5562725 A JP S5562725A JP 13093979 A JP13093979 A JP 13093979A JP 13093979 A JP13093979 A JP 13093979A JP S5562725 A JPS5562725 A JP S5562725A
Authority
JP
Japan
Prior art keywords
silicon substrate
diffused region
forming narrow
narrow diffused
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13093979A
Other languages
English (en)
Other versions
JPS6250969B2 (ja
Inventor
Tsuu Hou Aabingu
Raizuman Jieikabu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5562725A publication Critical patent/JPS5562725A/ja
Publication of JPS6250969B2 publication Critical patent/JPS6250969B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)
JP13093979A 1978-11-03 1979-10-12 Method of forming narrow diffused region on silicon substrate Granted JPS5562725A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/957,599 US4209350A (en) 1978-11-03 1978-11-03 Method for forming diffusions having narrow dimensions utilizing reactive ion etching

Publications (2)

Publication Number Publication Date
JPS5562725A true JPS5562725A (en) 1980-05-12
JPS6250969B2 JPS6250969B2 (ja) 1987-10-28

Family

ID=25499826

Family Applications (2)

Application Number Title Priority Date Filing Date
JP13093979A Granted JPS5562725A (en) 1978-11-03 1979-10-12 Method of forming narrow diffused region on silicon substrate
JP60181182A Granted JPS61159768A (ja) 1978-11-03 1985-08-20 電界効果トランジスタの製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP60181182A Granted JPS61159768A (ja) 1978-11-03 1985-08-20 電界効果トランジスタの製造方法

Country Status (6)

Country Link
US (1) US4209350A (ja)
EP (1) EP0010633B1 (ja)
JP (2) JPS5562725A (ja)
CA (1) CA1120610A (ja)
DE (1) DE2963852D1 (ja)
IT (1) IT1164518B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6362270A (ja) * 1986-08-28 1988-03-18 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン ポリシリコンのリボンを具備するバイポ−ラトランジスタの製造

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US4319932A (en) * 1980-03-24 1982-03-16 International Business Machines Corporation Method of making high performance bipolar transistor with polysilicon base contacts
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4513303A (en) * 1980-07-08 1985-04-23 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuit
US4488162A (en) * 1980-07-08 1984-12-11 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
JPS5758356A (en) * 1980-09-26 1982-04-08 Toshiba Corp Manufacture of semiconductor device
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
NL188432C (nl) * 1980-12-26 1992-06-16 Nippon Telegraph & Telephone Werkwijze voor het vervaardigen van een mosfet.
US4438556A (en) * 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
US4414737A (en) * 1981-01-30 1983-11-15 Tokyo Shibaura Denki Kabushiki Kaisha Production of Schottky barrier diode
US4691435A (en) * 1981-05-13 1987-09-08 International Business Machines Corporation Method for making Schottky diode having limited area self-aligned guard ring
JPS581878A (ja) * 1981-06-26 1983-01-07 Fujitsu Ltd 磁気バブルメモリ素子の製造方法
JPS5848936A (ja) * 1981-09-10 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
US4430791A (en) * 1981-12-30 1984-02-14 International Business Machines Corporation Sub-micrometer channel length field effect transistor process
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4445267A (en) * 1981-12-30 1984-05-01 International Business Machines Corporation MOSFET Structure and process to form micrometer long source/drain spacing
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
JPS58151390A (ja) * 1982-02-16 1983-09-08 ザ・ベンデイツクス・コ−ポレ−シヨン 非結晶質基板上に単結晶膜を形成する方法
US4712125A (en) * 1982-08-06 1987-12-08 International Business Machines Corporation Structure for contacting a narrow width PN junction region
US4507171A (en) * 1982-08-06 1985-03-26 International Business Machines Corporation Method for contacting a narrow width PN junction region
US4464212A (en) * 1982-12-13 1984-08-07 International Business Machines Corporation Method for making high sheet resistivity resistors
JPS59138379A (ja) * 1983-01-27 1984-08-08 Toshiba Corp 半導体装置の製造方法
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4641170A (en) * 1983-12-12 1987-02-03 International Business Machines Corporation Self-aligned lateral bipolar transistors
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4671830A (en) * 1984-01-03 1987-06-09 Xerox Corporation Method of controlling the modeling of the well energy band profile by interdiffusion
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4666557A (en) * 1984-12-10 1987-05-19 Ncr Corporation Method for forming channel stops in vertical semiconductor surfaces
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
US4714686A (en) * 1985-07-31 1987-12-22 Advanced Micro Devices, Inc. Method of forming contact plugs for planarized integrated circuits
US4843023A (en) * 1985-09-25 1989-06-27 Hewlett-Packard Company Process for forming lightly-doped-drain (LDD) without extra masking steps
GB8527062D0 (en) * 1985-11-02 1985-12-04 Plessey Co Plc Mos transistor manufacture
JPS62277745A (ja) * 1986-05-27 1987-12-02 Toshiba Corp 半導体集積回路
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
JPH0650741B2 (ja) * 1986-12-26 1994-06-29 富士通株式会社 半導体装置とその製造方法
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
JPH0766968B2 (ja) * 1987-08-24 1995-07-19 株式会社日立製作所 半導体装置及びその製造方法
US5179034A (en) * 1987-08-24 1993-01-12 Hitachi, Ltd. Method for fabricating insulated gate semiconductor device
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
DE3879186D1 (de) * 1988-04-19 1993-04-15 Ibm Verfahren zur herstellung von integrierten halbleiterstrukturen welche feldeffekttransistoren mit kanallaengen im submikrometerbereich enthalten.
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
US5064773A (en) * 1988-12-27 1991-11-12 Raytheon Company Method of forming bipolar transistor having closely spaced device regions
US5026663A (en) * 1989-07-21 1991-06-25 Motorola, Inc. Method of fabricating a structure having self-aligned diffused junctions
US5116778A (en) * 1990-02-05 1992-05-26 Advanced Micro Devices, Inc. Dopant sources for cmos device
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US5175606A (en) * 1990-08-27 1992-12-29 Taiwan Semiconductor Manufacturing Company Reverse self-aligned BiMOS transistor integrated circuit
US5071780A (en) * 1990-08-27 1991-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse self-aligned transistor integrated circuit
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US5028557A (en) * 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
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US6372589B1 (en) * 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6362270A (ja) * 1986-08-28 1988-03-18 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン ポリシリコンのリボンを具備するバイポ−ラトランジスタの製造

Also Published As

Publication number Publication date
JPH0347577B2 (ja) 1991-07-19
JPS6250969B2 (ja) 1987-10-28
US4209350A (en) 1980-06-24
EP0010633A1 (de) 1980-05-14
IT1164518B (it) 1987-04-15
EP0010633B1 (de) 1982-10-13
IT7926808A0 (it) 1979-10-26
JPS61159768A (ja) 1986-07-19
CA1120610A (en) 1982-03-23
DE2963852D1 (en) 1982-11-18

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