[go: up one dir, main page]

JPS5559746A - Semiconductor device and its mounting circuit device - Google Patents

Semiconductor device and its mounting circuit device

Info

Publication number
JPS5559746A
JPS5559746A JP13163478A JP13163478A JPS5559746A JP S5559746 A JPS5559746 A JP S5559746A JP 13163478 A JP13163478 A JP 13163478A JP 13163478 A JP13163478 A JP 13163478A JP S5559746 A JPS5559746 A JP S5559746A
Authority
JP
Japan
Prior art keywords
package
electrode
lsi
wiring
wiring substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13163478A
Other languages
Japanese (ja)
Other versions
JPS6220701B2 (en
Inventor
Kanji Otsuka
Masao Sekihashi
Tamotsu Usami
Michiaki Furukawa
Fumiyuki Kobayashi
Masakatsu Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13163478A priority Critical patent/JPS5559746A/en
Publication of JPS5559746A publication Critical patent/JPS5559746A/en
Publication of JPS6220701B2 publication Critical patent/JPS6220701B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To better radiation, by sealing a semiconductor element chip to a ceramic laminating type lead-less package, and by ensuring connection with a wiring substrate by mounting a conductor terminal for external connection at the wire bonding surface side in a shape that is higher than an upper surface of the package.
CONSTITUTION: A LSI chip 10 is connected onto a metallized portion 5, which is plated with gold, of a ceramic laminating type package 1, and pads on LSI wiring and metallized patterns 6 are bonded by means of gold wires 11. A cover 12, which coefficient of thermal expansion is closely resemble to ceramics, is connected onto a metallized portion 7, and seals the portion. When the cover 12 is mounted and the package is completed, the upper surface is located at the side lower than a surface of an electrode 8 installed being connected to a through hole metallized portion 9. The package is joined in a lead-less shape while directing the electrode 8 to a lower surface and opposing it to a wiring electrode 14 of a wiring substrate 15. A LSI is efficiently radiated from the back of the package positioned at a surface opposite to the wiring substrate 15. Radiation fins 10 may be mounted.
COPYRIGHT: (C)1980,JPO&Japio
JP13163478A 1978-10-27 1978-10-27 Semiconductor device and its mounting circuit device Granted JPS5559746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13163478A JPS5559746A (en) 1978-10-27 1978-10-27 Semiconductor device and its mounting circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13163478A JPS5559746A (en) 1978-10-27 1978-10-27 Semiconductor device and its mounting circuit device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP8636285A Division JPS60258932A (en) 1985-04-24 1985-04-24 Semiconductor devices and their circuit devices
JP29200587A Division JPS63146455A (en) 1987-11-20 1987-11-20 Semiconductor device and circuit device thereof

Publications (2)

Publication Number Publication Date
JPS5559746A true JPS5559746A (en) 1980-05-06
JPS6220701B2 JPS6220701B2 (en) 1987-05-08

Family

ID=15062629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13163478A Granted JPS5559746A (en) 1978-10-27 1978-10-27 Semiconductor device and its mounting circuit device

Country Status (1)

Country Link
JP (1) JPS5559746A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745262A (en) * 1980-09-01 1982-03-15 Fujitsu Ltd Sealing and fitting structure of semiconductor device
JPS59151443A (en) * 1983-02-17 1984-08-29 Fujitsu Ltd semiconductor equipment
JPS59198739A (en) * 1983-04-26 1984-11-10 Nec Corp Chipcarrier
JPH0189752U (en) * 1988-12-08 1989-06-13
US6652290B2 (en) 1999-03-18 2003-11-25 International Business Machines Corporation Connecting devices and method for interconnecting circuit components

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148377A (en) * 1978-05-15 1979-11-20 Ngk Spark Plug Co Leadless package for attaching semiconductor chip
JPS5521154A (en) * 1978-08-03 1980-02-15 Ngk Insulators Ltd Ceramic package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148377A (en) * 1978-05-15 1979-11-20 Ngk Spark Plug Co Leadless package for attaching semiconductor chip
JPS5521154A (en) * 1978-08-03 1980-02-15 Ngk Insulators Ltd Ceramic package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745262A (en) * 1980-09-01 1982-03-15 Fujitsu Ltd Sealing and fitting structure of semiconductor device
JPS634350B2 (en) * 1980-09-01 1988-01-28 Fujitsu Ltd
JPS59151443A (en) * 1983-02-17 1984-08-29 Fujitsu Ltd semiconductor equipment
JPS59198739A (en) * 1983-04-26 1984-11-10 Nec Corp Chipcarrier
JPH0189752U (en) * 1988-12-08 1989-06-13
JPH0536275Y2 (en) * 1988-12-08 1993-09-14
US6652290B2 (en) 1999-03-18 2003-11-25 International Business Machines Corporation Connecting devices and method for interconnecting circuit components

Also Published As

Publication number Publication date
JPS6220701B2 (en) 1987-05-08

Similar Documents

Publication Publication Date Title
US5646828A (en) Thin packaging of multi-chip modules with enhanced thermal/power management
JPH0445981B2 (en)
KR960705357A (en) Semiconductor devices
KR970013236A (en) Chip Scale Package with Metal Circuit Board
TW358230B (en) Semiconductor package
JPH03225854A (en) Semiconductor device and manufacture thereof
GB2136203B (en) Through-wafer integrated circuit connections
JPS5559746A (en) Semiconductor device and its mounting circuit device
JPS57126154A (en) Lsi package
JPS6220707B2 (en)
JP2727435B2 (en) Thin ball grid array semiconductor package with externally exposed heat sink attached
JPH04114455A (en) Semiconductor device and its mounting structure
JPS61137349A (en) Semiconductor device
JPH1032300A (en) Lead frame, semiconductor device and manufacture thereof
EP0081419A3 (en) High lead count hermetic mass bond integrated circuit carrier
US6265769B1 (en) Double-sided chip mount package
JPS57202747A (en) Electronic circuit device
JPS6066842A (en) Semiconductor device
KR950006441Y1 (en) High heat semiconductor package
JPS6329960A (en) Lead frame for resin-sealed semiconductor devices
JPS53110371A (en) Ceramic package type semiconductor device
JPS6020939Y2 (en) Substrate for semiconductor device package
JP2822446B2 (en) Hybrid integrated circuit device
JPH06120396A (en) Semiconductor device
JPH05315470A (en) Multichip module